A 256K dynamic random access memory

• Published in: IEEE journal of solid-state circuits 1982-10, Vol.17 (5), p.857-862
• Main Authors: Benevit, C.A., Cassard, J.M., Dimmler, K.J., Dumbri, A.C., Mound, M.G., Prockyk, F.J., Rosenzweig, W., Yanof, A.W.
• Format: Article
• Language: English
• Subjects: Capacitance; Decoding; DRAM chips; Electronics packaging; Manufacturing processes; Measurement standards; MOS devices; Power dissipation; Process design; Silicides
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.1982.1051831

A 5 V 256K/spl times/1 bit NMOS dynamic RAM employing redundancy is described. Using 2.3 /spl mu/m design rules, the cell is laid out in a folded bit line configuration having a row pitch of 6.5 /spl mu/m and a sense-amplifier pitch of 18 /spl mu/m. Tantalum silicide/polysilicon is used as the second polysilicon level to reduce the row line time constant. A storage capacitance of 60 fF and the Hi-C cell structure provides this memory with high alpha-particle insensitivity. The die measures 4.66/spl times/11.65 mm, and fits into a standard 0.3 in wide 16-pin DIP. The memory operates with 256 refresh cycles with a 4 ms refresh time. Typical RE/CE access times are 105/45 ns with an active power dissipation of 250 MW. Typical standby power is less than 20 mW. The part is compatible with the present Western Electric 5 V 64K part.