A 10K-Gate CMOS Gate Array Based on a Gate Isolation Structure

This paper describes an effect of the "gate isolation" technique and its application to a 10K-gate CMOS gate-array VLSI chip. This gate array is fabricated using a 2-/spl mu/m n-well CMOS technology, with double-level metallization. As an example, a 32-bit parallel array multiplier is desi...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1985-02, Vol.20 (1), p.413-417
Main Authors: Sakashita, K., Ueda, M., Arakawa, T., Asai, S., Fujimura, T., Ohkura, I.
Format: Article
Language:English
Subjects:
Aluminum
CMOS logic circuits
CMOS technology
Costs
Design automation
Isolation technology
Large scale integration
Logic arrays
Very large scale integration
Wiring
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Summary:This paper describes an effect of the "gate isolation" technique and its application to a 10K-gate CMOS gate-array VLSI chip. This gate array is fabricated using a 2-/spl mu/m n-well CMOS technology, with double-level metallization. As an example, a 32-bit parallel array multiplier is designed using a fully automatic CAD system. The density of CMOS gate arrays using gate isolation is estimated to be 1.10 to 1.26 times greater than that of the arrays using several types of oxide isolation, when implementing circuits with complexities on the order of 10K gates.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.1985.1052322