Computer-aided design in VLSI device development

Computer-aided design (CAD) has been used extensively in the development of VLSI MOS technology at Hewlett-Packard Laboratory. The CAD system for MOS device design is described. The development of the p-channel transistor with submicrometer channel length, trench isolation in CMOS, and side-wall-mas...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1985-04, Vol.20 (2), p.495-500
Main Authors: Cham, K.M., Oh, S.-Y., Moll, J.L.
Format: Article
Language:English
Subjects:
Applied sciences
Circuit simulation
CMOS technology
Design automation
Electronics
Exact sciences and technology
Integrated circuit interconnections
Integrated circuits
Isolation technology
Laboratories
MOS devices
Nonhomogeneous media
Parasitic capacitance
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Very large scale integration
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Summary:Computer-aided design (CAD) has been used extensively in the development of VLSI MOS technology at Hewlett-Packard Laboratory. The CAD system for MOS device design is described. The development of the p-channel transistor with submicrometer channel length, trench isolation in CMOS, and side-wall-masked isolation (SWAMI) for VLSI technology are then presented, followed by a discussion of the techniques used in the simulation of parasitic capacitances in multilayer interconnects for circuit performance evaluations.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.1985.1052335