A CMOS Four-Quadrant Analog Multiplier

A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the square-law characteristics of the MOS transistor. Two versions have been realized. The first has a linearity better than 0.14 percent for an output current swing of 36 percent of the suppl...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1986-06, Vol.21 (3), p.430-435
Main Authors: Bult, K., Wallinga, H.
Format: Article
Language:English
Subjects:
Adaptive filters
Applied sciences
Bandwidth
Circuit properties
Circuits
CMOS technology
Converters
Current supplies
Digital circuits
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Geometry
Linearity
MOSFETs
Voltage
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Summary:A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the square-law characteristics of the MOS transistor. Two versions have been realized. The first has a linearity better than 0.14 percent for an output current swing of 36 percent of the supply current and a bandwidth from dc to 1 MHz. The second version has floating inputs, a linearity of 0.4 percent at an output current swing of 40 percent of the supply current and a bandwidth from dc to above 4.5 MHz.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.1986.1052546