A noise optimization technique for integrated low-noise amplifiers

Based on measured four-noise parameters and two-port noise theory, considerations for noise optimization of integrated low-noise amplifier (LNA) designs are presented. If arbitrary values of source impedance are allowed, optimal noise performance of the LNA is obtained by adjusting the source degene...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2002-08, Vol.37 (8), p.994-1002
Main Authors: Jung-Suk Goo, Hee-Tae Ahn, Ladwig, D.J., Zhiping Yu, Lee, T.H., Dutton, R.W.
Format: Article
Language:English
Subjects:
Amplifiers
Circuits
CMOS
CMOS technology
Design optimization
Geometry
Impedance
Inductance
Low-noise amplifiers
Noise
Noise figure
Noise levels
Noise measurement
Optimization
Power amplifiers
Power supplies
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Summary:Based on measured four-noise parameters and two-port noise theory, considerations for noise optimization of integrated low-noise amplifier (LNA) designs are presented. If arbitrary values of source impedance are allowed, optimal noise performance of the LNA is obtained by adjusting the source degeneration inductance. Even for a fixed source impedance, the integrated LNA can achieve near NF/sub min/ by choosing an appropriate device geometry along with an optimal bias condition. An 800 MHz LNA has been implemented in a standard 0.24 /spl mu/m CMOS technology. The amplifier possesses a 0.9 dB noise figure with a 7.1 dBm third-order input intercept point, while drawing 7.5 mW from a 2.0 V power supply, demonstrating that the proposed methodology can accurately predict noise performance of integrated LNA designs.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2002.800956