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A 64-MHz clock-rate ΣΔ ADC with 88-dB SNDR and -105-dB IM3 distortion at a 1.5-MHz signal frequency
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Published in: | IEEE journal of solid-state circuits 2002-12, Vol.37 (12), p.1653-1661 |
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Main Authors: | , |
Format: | Article |
Language: | English |
Citations: | Items that this one cites Items that cite this one |
Online Access: | Get full text |
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ISSN: | 0018-9200 |
DOI: | 10.1109/JSSC.2002.804358 |