Latch-up ring design guidelines to improve electrostatic discharge (ESD) protection scheme efficiency

In this paper, we show how latch-up guard rings, surrounding electrostatic discharges (ESD) protection devices, can reduce the overall performance of the ESD protection scheme. This issue is addressed by TCAD simulation and experimental results. Design guidelines to cope with this problem are propos...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2004-10, Vol.39 (10), p.1778-1782
Main Authors: Tremouilles, D., Bafleur, M., Bertrand, G., Nolhier, N., Mauran, N., Lescouzeres, L.
Format: Article
Language:English
Subjects:
Applied sciences
Circuit simulation
Circuit testing
Circuits
Clamps
CMOS technology
Design. Technologies. Operation analysis. Testing
Devices
Electronics
Electrostatic discharge
Electrostatic discharges
Exact sciences and technology
Guards
Guidelines
Integrated circuit technology
Integrated circuits
Latch-up
Protection
Rails
Robustness
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Simulation
Testing, measurement, noise and reliability
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Description
Summary:In this paper, we show how latch-up guard rings, surrounding electrostatic discharges (ESD) protection devices, can reduce the overall performance of the ESD protection scheme. This issue is addressed by TCAD simulation and experimental results. Design guidelines to cope with this problem are proposed.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2004.833764