A 0.18-/spl mu/m CMOS front-end processor for a Blu-Ray Disc recorder with an adaptive PRML

• Published in: IEEE journal of solid-state circuits 2005-01, Vol.40 (1), p.342-350
• Main Authors: Goang Seog Choi, Joo Seon Kim, Hyun Jeong Park, Young Jun Ahn, Hyun Soo Park, Jum Han Bae, In Sik Park, Dong Ho Shin
• Format: Article
• Language: English
• Subjects: 23 GB; Analog-digital conversion; Blu-Ray Disc (BD); CMOS; CMOS process; CMOS technology; data processor (DP); Digital control; Equalizers; error correction code (ECC); Error correction codes; FPBDR; high-definition television (HDTV); nonlinear; Oscillators; partial response maximum likelihood (PRML); Phase locked loops; phase-locked loop (PLL); radio frequency (RF); recorder; Servomechanisms; Signal design; symbol error rate (SER); system-on-chip (SOC); tilt margin
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2004.837933

This paper describes a front-end processor for Blu-Ray Disc (BD) recorder applications. It integrates a partial response maximum likelihood (PRML) block, a data processor (DP) block, and a servo block. The PRML includes an analog-to-digital converter (ADC) and two digitally controlled oscillators (DCO) for data phase-locked loop (PLL) and wobble PLL. A nonlinear equalizer is designed to compensate for high-frequency signal components without increasing inter-symbol interference (ISI). A Teaklite DSP, an ADC, and a digital-to-analog converter are embedded for servo controls. The functions of 17PP modem and error correction code (ECC) are also implemented. Due to the proposed nonlinear equalizer in PRML, less than 2 /spl times/ 10/sup -4/ of symbol-error rate (SER), defined in the Blu-Ray Disc format book, is achieved with tangential tilt margin of /spl plusmn/0.5/spl deg/. This system on a chip (SOC) is fabricated in 0.18-/spl mu/m one-poly five-metal CMOS technology. It contains 12 million transistors in a 50-mm/sup 2/ die and consumes 0.9 W with a channel clock of 132 MHz in 2/spl times/ playback mode.