A 2.4 GHz Low-Power Sixth-Order RF Bandpass \Delta\Sigma Converter in CMOS

• Published in: IEEE journal of solid-state circuits 2009-11, Vol.44 (11), p.2873-2880
• Main Authors: Ryckaert, J., Borremans, J., Verbruggen, B., Bos, L., Armiento, C., Craninckx, J., Van der Plas, G.
• Format: Article
• Language: English
• Subjects: Analog-to-digital converters; Band pass filters; Bandwidth; Clocks; CMOS integrated circuits; CMOS process; continuous-time Delta\Sigma modulation; Digital filters; direct RF sampling; Energy consumption; impulse-invariance transformation; Radio frequency; Resonator filters; Sampling methods
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2009.2028914

A sixth-order RF bandpass DeltaSigma ADC operating on the 2.4 GHz ISM band, which is suitable for RF digitization is presented. The bandpass loop filter is based on digitally programmable Gm-LC resonators that can be calibrated online to adjust the RF center frequency. By sampling below the input Nyquist frequency, the clock in the system was reduced to 3 GHz, allowing a large reduction of the power consumption. Implemented in a standard 90 nm CMOS process, the IC achieves 40 dB and 62 dB of SNDR and SFDR, respectively, on a 60 MHz bandwidth with 40 mW of power consumption leading to a FoM of 245 GHz/W (4.1 pJ/conversion step). This implementation paves a possible way towards direct RF digitization receiver architectures.