An Embedded 65 nm CMOS Baseband IQ 48 MHz-1 GHz Dual Tuner for DOCSIS 3.0

• Published in: IEEE journal of solid-state circuits 2009-12, Vol.44 (12), p.3511-3525
• Main Authors: Gatta, F., Gomez, R., Shin, Y.J., Hayashi, T., Hanli Zou, Chang, J.Y.C., Dauphinee, L., Jianhong Xiao, Chang, D.S.-H., Tai-Hong Chih, Brandolini, M., Dongsoo Koh, Hung, B.J.-J., Tao Wu, Introini, M., Cusmai, G., Zencir, E., Singor, F., Eberhart, H., Tan, L.K., Currivan, B., Lin He, Cangiane, P., Vorenkamp, P.
• Format: Article
• Language: English
• Subjects: 256 QAM; 64 QAM; ACI; Acoustic wave devices, piezoelectric and piezoresistive devices; ADC; Annex A; Annex B; Applied sciences; Bandwidth; Baseband; baseband IQ; cable modem; Cable TV; CATV tuners; Circuit properties; Circuits of signal characteristics conditioning (including delay circuits); CMOS; CMOS technology; CSO; CTB; DAC; DC offset loops; Design. Technologies. Operation analysis. Testing; direct digital frequency synthesizer (DDFS); DOCSIS 3.0; down-stream channels (DS); downstream power management (DPM); Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; harmonic rejection RF front-end (HR RFFE); image rejection; Integrated circuits; local oscillator (LO); low IF; Modems; noise figure (NF); Phase locked loops; Power harmonic filters; Quadrature amplitude modulation; SCTE40; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; set-top box; Signal convertors; Signal to noise ratio; signal-to-noise ratio (SNR); SOC; Tuners; variable-gain amplifier (VGA); variable-gain low-noise amplifier (VGLNA)
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2009.2032497

An embedded CMOS digital dual tuner for DOCSIS 3.0 and set-top box applications is presented. The dual tuner down-converts a total of ten 6 MHz Annex B channels or eight 8 MHz Annex A channels, for a maximum data rate of 320 Mb/s in Annex B and 400 Mb/s in Annex A mode. The dual tuner exceeds all the stringent SCTE 40 specifications over the 48-1004 MHz bandwidth, without using any external components or SAW filters. Enabling technologies are a harmonic rejection front-end, a low-noise high-frequency resolution phase-locked loop (PLL) and digital image rejection. To our knowledge this is the first reported multi-channel Broadband Tuner embedded in a DOCSIS 3.0 System on a Chip implemented in a 65 nm pure digital CMOS technology.