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An Embedded 65 nm CMOS Baseband IQ 48 MHz-1 GHz Dual Tuner for DOCSIS 3.0
An embedded CMOS digital dual tuner for DOCSIS 3.0 and set-top box applications is presented. The dual tuner down-converts a total of ten 6 MHz Annex B channels or eight 8 MHz Annex A channels, for a maximum data rate of 320 Mb/s in Annex B and 400 Mb/s in Annex A mode. The dual tuner exceeds all th...
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Published in: | IEEE journal of solid-state circuits 2009-12, Vol.44 (12), p.3511-3525 |
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creator | Gatta, F. Gomez, R. Shin, Y.J. Hayashi, T. Hanli Zou Chang, J.Y.C. Dauphinee, L. Jianhong Xiao Chang, D.S.-H. Tai-Hong Chih Brandolini, M. Dongsoo Koh Hung, B.J.-J. Tao Wu Introini, M. Cusmai, G. Zencir, E. Singor, F. Eberhart, H. Tan, L.K. Currivan, B. Lin He Cangiane, P. Vorenkamp, P. |
description | An embedded CMOS digital dual tuner for DOCSIS 3.0 and set-top box applications is presented. The dual tuner down-converts a total of ten 6 MHz Annex B channels or eight 8 MHz Annex A channels, for a maximum data rate of 320 Mb/s in Annex B and 400 Mb/s in Annex A mode. The dual tuner exceeds all the stringent SCTE 40 specifications over the 48-1004 MHz bandwidth, without using any external components or SAW filters. Enabling technologies are a harmonic rejection front-end, a low-noise high-frequency resolution phase-locked loop (PLL) and digital image rejection. To our knowledge this is the first reported multi-channel Broadband Tuner embedded in a DOCSIS 3.0 System on a Chip implemented in a 65 nm pure digital CMOS technology. |
doi_str_mv | 10.1109/JSSC.2009.2032497 |
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The dual tuner down-converts a total of ten 6 MHz Annex B channels or eight 8 MHz Annex A channels, for a maximum data rate of 320 Mb/s in Annex B and 400 Mb/s in Annex A mode. The dual tuner exceeds all the stringent SCTE 40 specifications over the 48-1004 MHz bandwidth, without using any external components or SAW filters. Enabling technologies are a harmonic rejection front-end, a low-noise high-frequency resolution phase-locked loop (PLL) and digital image rejection. To our knowledge this is the first reported multi-channel Broadband Tuner embedded in a DOCSIS 3.0 System on a Chip implemented in a 65 nm pure digital CMOS technology.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2009.2032497</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>256 QAM ; 64 QAM ; ACI ; Acoustic wave devices, piezoelectric and piezoresistive devices ; ADC ; Annex A ; Annex B ; Applied sciences ; Bandwidth ; Baseband ; baseband IQ ; cable modem ; Cable TV ; CATV tuners ; Circuit properties ; Circuits of signal characteristics conditioning (including delay circuits) ; CMOS ; CMOS technology ; CSO ; CTB ; DAC ; DC offset loops ; Design. Technologies. Operation analysis. Testing ; direct digital frequency synthesizer (DDFS) ; DOCSIS 3.0 ; down-stream channels (DS) ; downstream power management (DPM) ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Exact sciences and technology ; harmonic rejection RF front-end (HR RFFE) ; image rejection ; Integrated circuits ; local oscillator (LO) ; low IF ; Modems ; noise figure (NF) ; Phase locked loops ; Power harmonic filters ; Quadrature amplitude modulation ; SCTE40 ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; set-top box ; Signal convertors ; Signal to noise ratio ; signal-to-noise ratio (SNR) ; SOC ; Tuners ; variable-gain amplifier (VGA) ; variable-gain low-noise amplifier (VGLNA)</subject><ispartof>IEEE journal of solid-state circuits, 2009-12, Vol.44 (12), p.3511-3525</ispartof><rights>2015 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2009</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c353t-f7a329288b19f7f1d7917b865ee8fd19804c738d4e9c395718ed58d15c1caa453</citedby><cites>FETCH-LOGICAL-c353t-f7a329288b19f7f1d7917b865ee8fd19804c738d4e9c395718ed58d15c1caa453</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5342363$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,27923,27924,54795</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=22260151$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Gatta, F.</creatorcontrib><creatorcontrib>Gomez, R.</creatorcontrib><creatorcontrib>Shin, Y.J.</creatorcontrib><creatorcontrib>Hayashi, T.</creatorcontrib><creatorcontrib>Hanli Zou</creatorcontrib><creatorcontrib>Chang, J.Y.C.</creatorcontrib><creatorcontrib>Dauphinee, L.</creatorcontrib><creatorcontrib>Jianhong Xiao</creatorcontrib><creatorcontrib>Chang, D.S.-H.</creatorcontrib><creatorcontrib>Tai-Hong Chih</creatorcontrib><creatorcontrib>Brandolini, M.</creatorcontrib><creatorcontrib>Dongsoo Koh</creatorcontrib><creatorcontrib>Hung, B.J.-J.</creatorcontrib><creatorcontrib>Tao Wu</creatorcontrib><creatorcontrib>Introini, M.</creatorcontrib><creatorcontrib>Cusmai, G.</creatorcontrib><creatorcontrib>Zencir, E.</creatorcontrib><creatorcontrib>Singor, F.</creatorcontrib><creatorcontrib>Eberhart, H.</creatorcontrib><creatorcontrib>Tan, L.K.</creatorcontrib><creatorcontrib>Currivan, B.</creatorcontrib><creatorcontrib>Lin He</creatorcontrib><creatorcontrib>Cangiane, P.</creatorcontrib><creatorcontrib>Vorenkamp, P.</creatorcontrib><title>An Embedded 65 nm CMOS Baseband IQ 48 MHz-1 GHz Dual Tuner for DOCSIS 3.0</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>An embedded CMOS digital dual tuner for DOCSIS 3.0 and set-top box applications is presented. The dual tuner down-converts a total of ten 6 MHz Annex B channels or eight 8 MHz Annex A channels, for a maximum data rate of 320 Mb/s in Annex B and 400 Mb/s in Annex A mode. The dual tuner exceeds all the stringent SCTE 40 specifications over the 48-1004 MHz bandwidth, without using any external components or SAW filters. Enabling technologies are a harmonic rejection front-end, a low-noise high-frequency resolution phase-locked loop (PLL) and digital image rejection. To our knowledge this is the first reported multi-channel Broadband Tuner embedded in a DOCSIS 3.0 System on a Chip implemented in a 65 nm pure digital CMOS technology.</description><subject>256 QAM</subject><subject>64 QAM</subject><subject>ACI</subject><subject>Acoustic wave devices, piezoelectric and piezoresistive devices</subject><subject>ADC</subject><subject>Annex A</subject><subject>Annex B</subject><subject>Applied sciences</subject><subject>Bandwidth</subject><subject>Baseband</subject><subject>baseband IQ</subject><subject>cable modem</subject><subject>Cable TV</subject><subject>CATV tuners</subject><subject>Circuit properties</subject><subject>Circuits of signal characteristics conditioning (including delay circuits)</subject><subject>CMOS</subject><subject>CMOS technology</subject><subject>CSO</subject><subject>CTB</subject><subject>DAC</subject><subject>DC offset loops</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>direct digital frequency synthesizer (DDFS)</subject><subject>DOCSIS 3.0</subject><subject>down-stream channels (DS)</subject><subject>downstream power management (DPM)</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>harmonic rejection RF front-end (HR RFFE)</subject><subject>image rejection</subject><subject>Integrated circuits</subject><subject>local oscillator (LO)</subject><subject>low IF</subject><subject>Modems</subject><subject>noise figure (NF)</subject><subject>Phase locked loops</subject><subject>Power harmonic filters</subject><subject>Quadrature amplitude modulation</subject><subject>SCTE40</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>set-top box</subject><subject>Signal convertors</subject><subject>Signal to noise ratio</subject><subject>signal-to-noise ratio (SNR)</subject><subject>SOC</subject><subject>Tuners</subject><subject>variable-gain amplifier (VGA)</subject><subject>variable-gain low-noise amplifier (VGLNA)</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2009</creationdate><recordtype>article</recordtype><recordid>eNpdkE1LAzEQhoMoWD9-gHgJgt62ZvLRJEfd1rZSKbIK3kKaZKGy3dXEPeivN6XFg5cZhnnemZcXoQsgQwCibx-rqhxSQnQujHItD9AAhFAFSPZ2iAaEgCp0Bo7RSUrveeRcwQDN71o82ayC98HjkcDtBpdPywrf2xRWtvV4_oy5wk-znwLwdPaDx71t8EvfhojrLuLxsqzmFWZDcoaOatukcL7vp-j1YfJSzorFcjov7xaFY4J9FbW0jGqq1Ap0LWvwUoNcqZEIQdUetCLcSaY8D9oxLSSo4IXyIBw4a7lgp-hmd_cjdp99SF9ms04uNI1tQ9cnw0aMgSQkg1f_wPeuj232ZvJLSjUjPEOwg1zsUoqhNh9xvbHx2wAx22TNNlmzTdbsk82a6_1hm5xt6mhbt05_QkrpiICAzF3uuHUI4W8tGKdbj78sGXrT</recordid><startdate>20091201</startdate><enddate>20091201</enddate><creator>Gatta, F.</creator><creator>Gomez, R.</creator><creator>Shin, Y.J.</creator><creator>Hayashi, T.</creator><creator>Hanli Zou</creator><creator>Chang, J.Y.C.</creator><creator>Dauphinee, L.</creator><creator>Jianhong Xiao</creator><creator>Chang, D.S.-H.</creator><creator>Tai-Hong Chih</creator><creator>Brandolini, M.</creator><creator>Dongsoo Koh</creator><creator>Hung, B.J.-J.</creator><creator>Tao Wu</creator><creator>Introini, M.</creator><creator>Cusmai, G.</creator><creator>Zencir, E.</creator><creator>Singor, F.</creator><creator>Eberhart, H.</creator><creator>Tan, L.K.</creator><creator>Currivan, B.</creator><creator>Lin He</creator><creator>Cangiane, P.</creator><creator>Vorenkamp, P.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20091201</creationdate><title>An Embedded 65 nm CMOS Baseband IQ 48 MHz-1 GHz Dual Tuner for DOCSIS 3.0</title><author>Gatta, F. ; Gomez, R. ; Shin, Y.J. ; Hayashi, T. ; Hanli Zou ; Chang, J.Y.C. ; Dauphinee, L. ; Jianhong Xiao ; Chang, D.S.-H. ; Tai-Hong Chih ; Brandolini, M. ; Dongsoo Koh ; Hung, B.J.-J. ; Tao Wu ; Introini, M. ; Cusmai, G. ; Zencir, E. ; Singor, F. ; Eberhart, H. ; Tan, L.K. ; Currivan, B. ; Lin He ; Cangiane, P. ; Vorenkamp, P.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c353t-f7a329288b19f7f1d7917b865ee8fd19804c738d4e9c395718ed58d15c1caa453</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2009</creationdate><topic>256 QAM</topic><topic>64 QAM</topic><topic>ACI</topic><topic>Acoustic wave devices, piezoelectric and piezoresistive devices</topic><topic>ADC</topic><topic>Annex A</topic><topic>Annex B</topic><topic>Applied sciences</topic><topic>Bandwidth</topic><topic>Baseband</topic><topic>baseband IQ</topic><topic>cable modem</topic><topic>Cable TV</topic><topic>CATV tuners</topic><topic>Circuit properties</topic><topic>Circuits of signal characteristics conditioning (including delay circuits)</topic><topic>CMOS</topic><topic>CMOS technology</topic><topic>CSO</topic><topic>CTB</topic><topic>DAC</topic><topic>DC offset loops</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>direct digital frequency synthesizer (DDFS)</topic><topic>DOCSIS 3.0</topic><topic>down-stream channels (DS)</topic><topic>downstream power management (DPM)</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>harmonic rejection RF front-end (HR RFFE)</topic><topic>image rejection</topic><topic>Integrated circuits</topic><topic>local oscillator (LO)</topic><topic>low IF</topic><topic>Modems</topic><topic>noise figure (NF)</topic><topic>Phase locked loops</topic><topic>Power harmonic filters</topic><topic>Quadrature amplitude modulation</topic><topic>SCTE40</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>set-top box</topic><topic>Signal convertors</topic><topic>Signal to noise ratio</topic><topic>signal-to-noise ratio (SNR)</topic><topic>SOC</topic><topic>Tuners</topic><topic>variable-gain amplifier (VGA)</topic><topic>variable-gain low-noise amplifier (VGLNA)</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Gatta, F.</creatorcontrib><creatorcontrib>Gomez, R.</creatorcontrib><creatorcontrib>Shin, Y.J.</creatorcontrib><creatorcontrib>Hayashi, T.</creatorcontrib><creatorcontrib>Hanli Zou</creatorcontrib><creatorcontrib>Chang, J.Y.C.</creatorcontrib><creatorcontrib>Dauphinee, L.</creatorcontrib><creatorcontrib>Jianhong Xiao</creatorcontrib><creatorcontrib>Chang, D.S.-H.</creatorcontrib><creatorcontrib>Tai-Hong Chih</creatorcontrib><creatorcontrib>Brandolini, M.</creatorcontrib><creatorcontrib>Dongsoo Koh</creatorcontrib><creatorcontrib>Hung, B.J.-J.</creatorcontrib><creatorcontrib>Tao Wu</creatorcontrib><creatorcontrib>Introini, M.</creatorcontrib><creatorcontrib>Cusmai, G.</creatorcontrib><creatorcontrib>Zencir, E.</creatorcontrib><creatorcontrib>Singor, F.</creatorcontrib><creatorcontrib>Eberhart, H.</creatorcontrib><creatorcontrib>Tan, L.K.</creatorcontrib><creatorcontrib>Currivan, B.</creatorcontrib><creatorcontrib>Lin He</creatorcontrib><creatorcontrib>Cangiane, P.</creatorcontrib><creatorcontrib>Vorenkamp, P.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Gatta, F.</au><au>Gomez, R.</au><au>Shin, Y.J.</au><au>Hayashi, T.</au><au>Hanli Zou</au><au>Chang, J.Y.C.</au><au>Dauphinee, L.</au><au>Jianhong Xiao</au><au>Chang, D.S.-H.</au><au>Tai-Hong Chih</au><au>Brandolini, M.</au><au>Dongsoo Koh</au><au>Hung, B.J.-J.</au><au>Tao Wu</au><au>Introini, M.</au><au>Cusmai, G.</au><au>Zencir, E.</au><au>Singor, F.</au><au>Eberhart, H.</au><au>Tan, L.K.</au><au>Currivan, B.</au><au>Lin He</au><au>Cangiane, P.</au><au>Vorenkamp, P.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>An Embedded 65 nm CMOS Baseband IQ 48 MHz-1 GHz Dual Tuner for DOCSIS 3.0</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2009-12-01</date><risdate>2009</risdate><volume>44</volume><issue>12</issue><spage>3511</spage><epage>3525</epage><pages>3511-3525</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>An embedded CMOS digital dual tuner for DOCSIS 3.0 and set-top box applications is presented. The dual tuner down-converts a total of ten 6 MHz Annex B channels or eight 8 MHz Annex A channels, for a maximum data rate of 320 Mb/s in Annex B and 400 Mb/s in Annex A mode. The dual tuner exceeds all the stringent SCTE 40 specifications over the 48-1004 MHz bandwidth, without using any external components or SAW filters. Enabling technologies are a harmonic rejection front-end, a low-noise high-frequency resolution phase-locked loop (PLL) and digital image rejection. To our knowledge this is the first reported multi-channel Broadband Tuner embedded in a DOCSIS 3.0 System on a Chip implemented in a 65 nm pure digital CMOS technology.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/JSSC.2009.2032497</doi><tpages>15</tpages></addata></record> |
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subjects | 256 QAM 64 QAM ACI Acoustic wave devices, piezoelectric and piezoresistive devices ADC Annex A Annex B Applied sciences Bandwidth Baseband baseband IQ cable modem Cable TV CATV tuners Circuit properties Circuits of signal characteristics conditioning (including delay circuits) CMOS CMOS technology CSO CTB DAC DC offset loops Design. Technologies. Operation analysis. Testing direct digital frequency synthesizer (DDFS) DOCSIS 3.0 down-stream channels (DS) downstream power management (DPM) Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology harmonic rejection RF front-end (HR RFFE) image rejection Integrated circuits local oscillator (LO) low IF Modems noise figure (NF) Phase locked loops Power harmonic filters Quadrature amplitude modulation SCTE40 Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices set-top box Signal convertors Signal to noise ratio signal-to-noise ratio (SNR) SOC Tuners variable-gain amplifier (VGA) variable-gain low-noise amplifier (VGLNA) |
title | An Embedded 65 nm CMOS Baseband IQ 48 MHz-1 GHz Dual Tuner for DOCSIS 3.0 |
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