Discrete-Time Mixing Receiver Architecture for RF-Sampling Software-Defined Radio

• Published in: IEEE journal of solid-state circuits 2010-09, Vol.45 (9), p.1732-1745
• Main Authors: Zhiyu Ru, Klumperink, E A M, Nauta, B
• Format: Article
• Language: English
• Subjects: Amplifiers; anti-aliasing; Applied sciences; Architecture; Channels; Circuit properties; CMOS; CMOS integrated circuits; Computer architecture; continuous-time mixing; de-multiplexer; de-multiplexing; demodulation; Design. Technologies. Operation analysis. Testing; discrete-time mixing; downconversion; downconverter; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Harmonic analysis; harmonic rejection; Harmonics; Integrated circuits; interference; Microwave circuits, microwave integrated circuits, microwave transmission lines, submillimeter wave circuits; Mixers; mixing; Noise levels; Oversampling; phase shift; quadrature; Radio frequencies; Radio frequency; Radios; receiver; Receivers; Receivers & amplifiers; Rejection; RF sampling; Sampling; sampling receiver; SDR; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal convertors; SoC; software radio; software-defined radio; SWR; system-on-chip; Wideband; wideband receiver; wideband sampling
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2010.2053860

A discrete-time (DT) mixing architecture for RF-sampling receivers is presented. This architecture makes RF sampling more suitable for software-defined radio (SDR) as it achieves wideband quadrature demodulation and wideband harmonic rejection. The paper consists of two parts. In the first part, different downconversion techniques are classified and compared, leading to the definition of a DT mixing concept. The suitability of CT-mixing and RF-sampling receivers to SDR is also discussed. In the second part, we elaborate the DT-mixing architecture, which can be realized by de-multiplexing. Simulation shows a wideband 90° phase shift between I and Q outputs without systematic channel bandwidth limitation. Oversampling and harmonic rejection relaxes RF pre-filtering and reduces noise and interference folding. A proof-of-concept DT-mixing downconverter has been built in 65 nm CMOS, for 0.2 to 0.9 GHz RF band employing 8-times oversampling. It can reject 2nd to 6th harmonics by 40 dB typically and without systematic channel bandwidth limitation. Without an LNA, it achieves a gain of -0.5 to 2.5 dB, a DSB noise figure of 18 to 20 dB, an IIP3 = +10 dBm, and an IIP2 = +53 dBm, while consuming less than 19 mW including multiphase clock generation.