A 2 \,\times\, 25-Gb/s Receiver With 2:5 DMUX for 100-Gb/s Ethernet

A 2 × 25-Gb/s receiver for 100-Gb Ethernet (100 GbE) has been implemented in 65-nm CMOS technology. A new regulation mechanism is applied to the limiting amplifier to minimize its gain and bandwidth variations. Two low-power full-rate CDRs (with a built-in clock generator) and a high-speed 2:5 DMUX...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2010-11, Vol.45 (11), p.2421-2432
Main Authors: Wu, Ke-Chung, Lee, Jri
Format: Article
Language:English
Subjects:
bandgap reference
Bandwidth
bit error rate (BER)
clock and data recovery (CDR)
clock multiplication unit (CMU)
Clocks
CMOS integrated circuits
demultiplexer (DMUX)
deskew circuit
divider
Gain
GbE
jitter tolerance
Limiting
limiting amplifier (LA)
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Receivers
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Summary:A 2 × 25-Gb/s receiver for 100-Gb Ethernet (100 GbE) has been implemented in 65-nm CMOS technology. A new regulation mechanism is applied to the limiting amplifier to minimize its gain and bandwidth variations. Two low-power full-rate CDRs (with a built-in clock generator) and a high-speed 2:5 DMUX circuit are integrated. Although only two channels are implemented, this receiver provides exactly the same operation as a four-channel one while dealing with independent channels. The prototype achieves bit error rate
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2010.2074291