A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology

This paper introduces a fully-integrated wireline transceiver operating at 40 Gb/s. The transmitter incorporates a 5-tap finite-inpulse response (FIR) filter with LC-based delay lines precisely adjusted by a closed-loop delay controller. The receiver employs a similar 3-tap FIR filter as an equalize...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2012-03, Vol.47 (3), p.627-640
Main Authors: CHEN, Ming-Shuan, SHIH, Yu-Nan, LIN, Chen-Lun, HUNG, Hao-Wei, LEE, Jri
Format: Article
Language:English
Subjects:
Applied sciences
Bandwidth
Circuit properties
Circuits of signal characteristics conditioning (including delay circuits)
Clock and data recovery (CDR)
Clocks
CMOS integrated circuits
Delay
Design. Technologies. Operation analysis. Testing
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
equalizer
Exact sciences and technology
Finite impulse response filter
finite-inpulse response (FIR) filter
Frequency filters
Integrated circuits
majority voting
Miscellaneous
Power transmission lines
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
transceiver (TRx)
Transceivers
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Summary:This paper introduces a fully-integrated wireline transceiver operating at 40 Gb/s. The transmitter incorporates a 5-tap finite-inpulse response (FIR) filter with LC-based delay lines precisely adjusted by a closed-loop delay controller. The receiver employs a similar 3-tap FIR filter as an equalizer front-end with digital adaptation, and a sub-rate clock and data recovery circuit using majority voting phase detection. The transceiver delivers 40-Gb/s 2 7 -1 PRBS data across a Rogers channel of 20 cm (19-dB loss at 20 GHz) with BER
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2011.2176635