A 130.7- \hbox^ 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology

A 32-Gb ReRAM test chip has been developed in a 24-nm process, with a diode as the selection device and metal oxide as the switching element. The memory array is constructed with cross-point architecture to allow multiple memory layers stacked above the supporting circuitry and minimize the circuit...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2014-01, Vol.49 (1), p.140-153
Main Authors: Tz-yi Liu, Tian Hong Yan, Scheuerlein, Roy, Yingchang Chen, Lee, Jeffrey KoonYee, Balakrishnan, Gopinath, Yee, Gordon, Zhang, Henry, Yap, Alex, Ouyang, Jingwen, Sasaki, Takahiko, Al-Shamma, Ali, Chen, Chinyu, Gupta, Mayank, Hilton, Greg, Kathuria, Achal, Lai, Vincent, Matsumoto, Masahide, Nigam, Anurag, Pai, Anil, Pakhale, Jayesh, Chang Hua Siau, Xiaoxia Wu, Yibo Yin, Nagel, Nicolas, Tanaka, Yoichiro, Higashitani, Masaaki, Minvielle, Tim, Gorla, Chandu, Tsukamoto, Takayuki, Yamaguchi, Takeshi, Okajima, Mutsumi, Okamura, Takayuki, Takase, Satoru, Inoue, Hirofumi, Fasoli, Luca
Format: Article
Language:English
Subjects:
3-D architecture
Arrays
Charge pump
cross-point
current compliance
leakage current compensation
Leakage currents
multiple-layer
nonvolatile memory
Registers
ReRAM
Sensors
sneak path
Switches
Transistors
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Summary:A 32-Gb ReRAM test chip has been developed in a 24-nm process, with a diode as the selection device and metal oxide as the switching element. The memory array is constructed with cross-point architecture to allow multiple memory layers stacked above the supporting circuitry and minimize the circuit area overhead. Die efficiency is further improved by sharing wordlines and bitlines between adjacent blocks. As the number of sense amplifiers under the memory array is limited, a pipelined array control scheme is adopted to compensate the performance impact while utilizing the fast switching time of ReRAM cells. With the chip current consumption being dominated by the array leakage and sensitive to array bias and operating conditions, a charge pump stage control scheme is introduced to dynamically adapt to the operating conditions for optimal power consumption. Smart Read during sensing and leakage current compensation scheme during programming are applied to the large-block architecture and achieve a chip density that is several orders of magnitude higher than prior ReRAM developments.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2013.2280296