Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits

In order to eliminate the limitation of a narrow frequency range of conventional resonant clocking, intermittent resonant clocking (IRC) is proposed for near/sub-threshold logic circuits. In this paper, IRC is applied to 0.37 V 32-bit adder array with latches and adder array with flip-flops fabricat...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2014-02, Vol.49 (2), p.536-544
Main Authors: Fuketa, Hiroshi, Nomura, Masahiro, Takamiya, Makoto, Sakurai, Takayasu
Format: Article
Language:English
Subjects:
Adders
Arrays
Clocks
LC resonance
Logic gates
near-threshold circuit
Resistance
resonant clocking
Resonant frequency
RLC circuits
subthreshold circuit
ultra-low power
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Summary:In order to eliminate the limitation of a narrow frequency range of conventional resonant clocking, intermittent resonant clocking (IRC) is proposed for near/sub-threshold logic circuits. In this paper, IRC is applied to 0.37 V 32-bit adder array with latches and adder array with flip-flops fabricated in a 40 nm CMOS process. Measurement results show that IRC reduces the clock power by 36% at 980 kHz and the clock leakage power by 81% compared with conventional non-resonant clocking when IRC is applied to the adder array with latches. The same power reduction is achieved when IRC is applied to the adder array with flip-flops. IRC can reduce the clock power at any clock frequency, which enables flexible selection of the clock frequency.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2013.2294172