A Fine-Grain Variation-Aware Dynamic -Hopping AVFS Architecture on a 32 nm GALS MPSoC

In order to optimize global energy efficiency in the context of dynamic process, voltage and temperature variations in advanced nodes, a fine-grain adaptive voltage and frequency scaling architecture is proposed for multiprocessor systems-on-chip (MPSoC), where each processing element is an independ...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2014-07, Vol.49 (7), p.1475-1486
Main Authors: Miro-Panades, Ivan, Beigne, Edith, Thonnart, Yvain, Alacoque, Laurent, Vivet, Pascal, Lesecq, Suzanne, Puschini, Diego, Molnos, Anca, Thabet, Farhat, Tain, Benoit, Ben Chehida, Karim, Engels, Sylvain, Wilson, Robin, Fuin, Didier
Format: Article
Language:English
Subjects:
Actuators
Adaptive voltage and frequency scaling (AVFS)
chip multiprocessor
Clocks
energy efficiency
globally asynchronous locally synchronous (GALS)
Hardware
Program processors
Sensors
Timing
Voltage control
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Summary:In order to optimize global energy efficiency in the context of dynamic process, voltage and temperature variations in advanced nodes, a fine-grain adaptive voltage and frequency scaling architecture is proposed for multiprocessor systems-on-chip (MPSoC), where each processing element is an independent voltage-frequency island. This architecture has been implemented on a 32 nm globally asynchronous locally-synchronous MPSoC. It shows up to 18.2% energy gains thanks to local adaptability compared with a global dynamic voltage and frequency scaling approach using 25% timing margins between slow and nominal process, by reducing margins to 60 ps of the real process. These gains are obtained for a total area overhead of 10% including local frequency/voltage actuators, sensors, and digital controller.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2014.2317137