A 4.5 mW CT Self-Coupled \Delta\Sigma Modulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation

• Published in: IEEE journal of solid-state circuits 2015-12, Vol.50 (12), p.2870-2879
• Main Authors: Ho, Chen-Yen, Liu, Cong, Lo, Chi-Lun, Tsai, Hung-Chieh, Wang, Tze-Chien, Lin, Yu-Hsin
• Format: Article
• Language: English
• Subjects: Analog-to-digital converter (ADC); Clocks; continuous-time delta-sigma modulator (CT DSM); continuous-time self-coupling (CTSC); Delays; excess loop delay (ELD) compensation; Latches; Modulation; Noise; Quantization (signal); Resistors
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2015.2475160

This paper presents a power-efficient single-loop continuous-time (CT) ΔΣ modulator (DSM) that achieves a SNDR of 90.4 dB over a 2.2 MHz signal bandwidth. The modulator uses a fourth-order feed-forward architecture incorporating the continuous-time self-coupling (CTSC) technique. Moreover, to reduce hardware area, this design utilizes the residual signal for excess loop delay (ELD) compensation. To improve linearity, low-ripple DAC latches and low toggle-rate dynamic element matching (DEM) algorithm are adopted. This DSM is fabricated in a 55 nm LP CMOS technology. Operating at 140 MHz sampling rate, the chip consumes 4.5 mW from power supplies of 1.2 V and 1.8 V. It achieves 90.4 dB SNDR and 92 dB dynamic range (DR) with a 2.2 MHz signal bandwidth, resulting in a Schreier FOM of 177.3 dB and 178.9 dB based on SNDR and DR, respectively. The chip area is 0.09 mm 2 .