A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation

• Published in: IEEE journal of solid-state circuits 2018-06, Vol.53 (6), p.1765-1779
• Main Authors: Nam, Jae-Won, Hassanpourghadi, Mohsen, Zhang, Aoyang, Chen, Mike Shuo-Wei
• Format: Article
• Language: English
• Subjects: Analog to digital conversion; Analog to digital converters; Capacitance; Clocks; CMOS; Cycle time; Interpolation; multi-bit/cycle; Power demand; Prototypes; Registers; Sampling; successive-approximation register analog-to-digital converter (SAR ADC); switched-capacitor circuit; time-interleaved (TI) ADC; Topology
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2018.2808244

This paper demonstrates a multi-bit/cycle successive-approximation register (SAR) analog-to-digital converter (ADC) architecture for low-power and high-speed operation. The proposed dual reference shifting and interpolation technique reduces the power and area overhead of the multi-bit/ cycle SAR architecture, allowing for a higher number of bit quantization for each conversion cycle and thus, a higher conversion rate. To prove the concept, a 12-bit 32-way time-interleaved 4-b/cycle SAR ADC prototype is fabricated in 65-nm CMOS technology. The ADC prototype can be configured with multiple sampling rates (1.6, 3.2, and 6.4 GS/s). It measures a peak effective number of bits (ENOB) of 10.9 bits at 6.4 GS/s and 9.4 ENOB at the maximum input frequency of 1 GHz. The prototype achieves a Schreier figure-of-merit (FOM Schreier ) of 154.9 dB at 6.4-GS/s sampling rate.