A 0.75-3.0-Gb/s Dual-Mode Temperature-Tolerant Referenceless CDR With a Deadzone-Compensated Frequency Detector

This paper proposes a 750-Mb/s to 3.0-Gb/s dual-mode (full and half rate) referenceless clock and data recovery (CDR) circuit in a 65-nm CMOS process. The dual-mode deadzone-compensated frequency detector (DC-FD) and the digital calibration of both bank and control voltage of voltage-controlled osci...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2018-10, Vol.53 (10), p.2994-3003
Main Authors: Jin, Jahoon, Jin, Xuefan, Jung, Jaehong, Kwon, Kiwon, Kim, Jintae, Chun, Jung-Hoon
Format: Article
Language:English
Subjects:
Bit error rate
Clock and data recovery (CDR)
Clocks
CMOS
Data recovery
deadzone compensation
Detectors
dual-mode
Electric potential
frequency acquisition
Frequency control
Frequency locked loops
Jitter
jitter tolerance (JTOL)
referenceless
Temperature compensation
Temperature distribution
Vibration
Video transmission
Voltage controlled oscillators
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Summary:This paper proposes a 750-Mb/s to 3.0-Gb/s dual-mode (full and half rate) referenceless clock and data recovery (CDR) circuit in a 65-nm CMOS process. The dual-mode deadzone-compensated frequency detector (DC-FD) and the digital calibration of both bank and control voltage of voltage-controlled oscillators (VCOs) allow precise frequency acquisition even with high input jitter. The dual-mode scheme extends supported data rates, and the temperature compensation technique allows uninterrupted video transmission with a bit error rate (BER) below 10 −12 over a wide temperature range from −20 °C to 120 °C.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2018.2856243