A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET

• Published in: IEEE journal of solid-state circuits 2019-01, Vol.54 (1), p.18-28
• Main Authors: Upadhyaya, Parag, Poon, Chi Fung, Lim, Siok Wei, Cho, Junho, Roldan, Arianne, Zhang, Wenfeng, Namkoong, Jin, Pham, Toan, Xu, Bruce, Lin, Winson, Zhang, Hongtao, Narang, Nakul, Tan, Kee Hian, Zhang, Geoff, Frans, Yohan, Chang, Ken
• Format: Article
• Language: English
• Subjects: Analog to digital converters; Bandwidth; Bit error rate; Continuous-time linear equalizer (CTLE); Crosstalk; Data recovery; decision feedback equalizer (DFE); Decision feedback equalizers; Digital signal processing; digital signal processing (DSP); Error correction; feed forward equalizer (FFE); four-level pulse-amplitude modulation (PAM-4) and nonreturn to zero (NRZ) transceiver; Gain; Optical signal processing; Pulse amplitude modulation; Receivers; time interleaved successive-approximation-register (SAR) analog to digital converter (ADC) (TI-ADC); Transceivers; voltage mode transmitter
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2018.2875091

The design of a dual-mode, 19-58-Gb/s four-level pulse-amplitude modulation (PAM-4) and 9.5-29-Gb/s nonreturn to zero (NRZ), transceiver in 16-nm FinFET is presented. The fully adaptive receiver consists of a multi-stage continuous time linear equalizer (CTLE), a configurable 32-way time-interleaved 3-to-7-bit successive-approximation-register (SAR) analog to digital converter (ADC), a 14-tap feed forward equalizer (FFE)/one-tap decision feedback equalizer (DFE) digital signal processing (DSP), and a baud-rate clock and data recovery (CDR). A four-tap voltage mode transmitter with two pre-cursor taps and one post-cursor tap, incorporates impedance control loop to meet return loss requirements while maintaining good PAM-4 level mismatch ratio of 0.98. At 56 Gb/s, the transceiver achieves the