3-D NAND Flash Value-Aware SSD: Error-Tolerant SSD Without ECCs for Image Recognition

• Published in: IEEE journal of solid-state circuits 2019-06, Vol.54 (6), p.1800-1811
• Main Authors: Deguchi, Yoshiaki, Nakamura, Toshiki, Hayakawa, Atsuna, Takeuchi, Ken
• Format: Article
• Language: English
• Subjects: Artificial neural networks; Bit error rate; Computer memory; Data storage; Decoding; Deep neural network (DNN); Error correcting codes; Error correction; Error correction codes; Error reduction; Floating point arithmetic; Format; Image enhancement; Image recognition; Integrated circuit reliability; Network reliability; Object recognition; Power consumption; Power demand; reliability; Solid state devices; solid-state drive (SSD); Threshold voltage; vertical 3-D NAND flash memory
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2019.2900866

This paper proposes Value-Aware solid-state drive (SSD) with fast access speed and low power consumption by eliminating error-correcting code (ECC). Value-Aware SSD utilizes the error tolerance of image recognition application using a deep neural network (DNN) to enhance reliability. In a previous paper, which proposes Value-Aware SSD, fast ECC decoder is implemented and SSD is evaluated with the 32-bit floating-point data format. On the other hand, in this paper, the proposed Value-Aware SSD is analyzed with 32-bit and 8-bit fixed-point data format and achieves the higher reliability even without ECC by newly proposed two techniques, Critical Bit Error Reduction (CBER) and Middle & Lower Page Error Reduction (M&L-PER). CBER and M&L-PER are proposed for 32-bit and 8-bit data format of application, respectively. These techniques modulate the threshold voltage ( V_{\mathrm {TH}} ) distribution of memory cells by recognizing the importance of each stored bit. By proposed CBER, as much as 15% bit error rate (BER) of NAND flash is allowed while the application provides high image recognition accuracy. Even if bit precision is truncated to 8 bit, 3.9% BER is accepted by M&L-PER. The fast read access and low power consumption are realized because ECC is not required. Finally, this paper analyzes the Value-Aware techniques with 3-D multi-level cell (MLC) NAND flash to compare the effects for 3D-MLC and triple-level cell (TLC) NAND flash.