A 320-fs RMS Jitter and - 75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC

• Published in: IEEE journal of solid-state circuits 2019-09, Vol.54 (9), p.2501-2512
• Main Authors: Seong, Taeho, Lee, Yongsun, Yoo, Seyeon, Choi, Jaehyouk
• Format: Article
• Language: English
• Subjects: Clocks; CMOS; Converters; Digital phase-locked loop (DPLL); Frequency measurement; Jitter; Oscillators; Phase locked loops; Phase locked systems; Power consumption; Quantization (signal); reference spur; ring digitally controlled oscillator (DCO); time-to-digital converter (TDC); Timing; Vibration
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2019.2918940

This paper presents a ring-type, digitally controlled oscillator (DCO)-based integer- {N} digital phase-locked loop (DPLL) that can achieve low jitter and low reference spur concurrently. In order to minimize the quantization error, while consuming a small amount of power, this work presents an optimal-threshold (OT) time-to-digital converter (TDC). The thresholds of the OT TDC and the phase-correction gain of the loop are corrected continuously in the background. The PLL was fabricated in a 65-nm CMOS process and its measured rms jitter integrated from 1 kHz to 100 MHz and the reference spur of a 2.4-GHz frequency were 320 fs and −75 dBc, respectively. Through measurement, they were verified to be maintained robustly over temperature and supply variations. The active area was 0.055 mm 2 , and the power consumption was 6.0 mW.