Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14-nm SOI CMOS

A distributed network of low-dropout (LDO) microregulators (uREGs) senses and corrects the voltages at multiple points on a power supply grid in a multi-core microprocessor to reduce errors due to IR drops. A voltage regulator controller (VREGC) compares the voltages at various points on the grid to...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2020-03, Vol.55 (3), p.731-743
Main Authors: Perez, Miguel E., Sperling, Michael A., Bulzacchelli, John F., Toprak-Deniz, Zeynep, Diemoz, Timothy E.
Format: Article
Language:English
Subjects:
Charge pump
Charge pumps
CMOS
Computer networks
Current distribution
Current efficiency
Current mirrors
distributed regulator
IR drop
load sharing
low dropout (LDO)
Microprocessors
multi-sector
multi-sense
Nanosecond response
Offsets
Power efficiency
Power supplies
Regulation
Regulators
Stress concentration
System-on-chip
Voltage
Voltage control
Voltage regulators
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Summary:A distributed network of low-dropout (LDO) microregulators (uREGs) senses and corrects the voltages at multiple points on a power supply grid in a multi-core microprocessor to reduce errors due to IR drops. A voltage regulator controller (VREGC) compares the voltages at various points on the grid to a programmable reference and delivers a set of corrective 2-b up/down (UP/DN) codes (global feedback) to the distributed uREGs across the core. Inside each uREG, the UP/DN codes control a local charge pump that sets the reference for an asynchronous comparator that turns on and off a pMOS passgate with a sub-nanosecond response. To mitigate the self-generated ripple, hybrid fast/slow passgate control is employed, whereby a parallel pMOS passgate with a slew-rate-limited gate drive is used to supply the dc portion of the load current. The distributed regulator architecture includes a scheme for limiting the degree of load-sharing imbalances among its uREGs due to the VREGC comparator offsets. Adding a switched-capacitor (SC) accelerator to the charge pump of each uREG speeds up the outputvoltage transitions by up to 17× for greater dynamic voltage and frequency scaling (DVFS) savings. Line and load regulations are 9 mV/V and 1.1 mV/A, respectively. The regulator achieves a peak power efficiency of 95.2% and a peak current efficiency of 99.1%. It reaches a peak power density of 82.3 W/mm 2 .
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2019.2956413