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A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping
Noise-shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) using passive loop filters have drawn the increasing attentions owing to their simplicity, low power, zero static current, and PVT robustness. However, prior works show the limited resolution because of tw...
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Published in: | IEEE journal of solid-state circuits 2021-11, Vol.56 (11), p.3412-3423 |
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creator | Liu, Jiaxin Wang, Xing Gao, Zijie Zhan, Mingtao Tang, Xiyuan Hsu, Chen-Kai Sun, Nan |
description | Noise-shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) using passive loop filters have drawn the increasing attentions owing to their simplicity, low power, zero static current, and PVT robustness. However, prior works show the limited resolution because of two main challenges: the thermal noise and the digital-to-analog converter (DAC) mismatch. This article presents a high-resolution full passive NS SAR ADC. It uses an efficient NS filter architecture that realizes a 4 \times passive gain and the passive summation, significantly reducing the total thermal noise. It also realizes the second-order DAC mismatch error shaping (MES) that is tone-free. A digital prediction is proposed to solve the signal-range loss issue caused by the MES, recovering the ADC input signal range to the full swing. A prototype NS SAR ADC is implemented in 40-nm CMOS process. It measures 90.5-dB signal-to-noise-and-distortion ratio (SNDR) and 94.3-dB dynamic range (DR) over 40-kHz bandwidth without any calibration. It consumes 67.4 \mu \text{W} power from a 1.1-V supply and occupies 0.061 mm 2 area. |
doi_str_mv | 10.1109/JSSC.2021.3087661 |
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fullrecord | <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_crossref_primary_10_1109_JSSC_2021_3087661</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>9459709</ieee_id><sourcerecordid>2586590887</sourcerecordid><originalsourceid>FETCH-LOGICAL-c208t-96968e5a3d59b0d9bc422ab2ad7514826ea152b446b36ddaaca820fda9d0ec0b3</originalsourceid><addsrcrecordid>eNo9kMtOwzAQRS0EEqXwAYiNJdYuYydO7GVIWx4qDxEQ7KJJ7FKjkhQ7RWLNR_BB_BitWrEaXencO9Ih5JjDgHPQZ9dFkQ8ECD6IQKVJwndIj0upGE-jl13SA-CKaQGwTw5CeFvFOFa8R74zqoGZc1bcDh9ojnNXeexc27Cxt5aOl_P5F73HENynpbetC5YVM1y45pUW2QPNhjl9dt2Mxr8__9gFuoZiY2hh67Yx7M4b6-kwy-mNC-_Y1TM68r71dLt0SPamOA_2aHv75Gk8eswv2eTu4irPJqwWoDqmE50oKzEyUldgdFXHQmAl0KSSx0okFrkUVRwnVZQYg1ijEjA1qA3YGqqoT043uwvffixt6Mq3dumb1ctSSJVIDUqlK4pvqNq3IXg7LRfevaP_KjmUa9fl2nW5dl1uXa86J5uOs9b-8zqWOgUd_QHSbnlP</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2586590887</pqid></control><display><type>article</type><title>A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping</title><source>IEEE Xplore (Online service)</source><creator>Liu, Jiaxin ; Wang, Xing ; Gao, Zijie ; Zhan, Mingtao ; Tang, Xiyuan ; Hsu, Chen-Kai ; Sun, Nan</creator><creatorcontrib>Liu, Jiaxin ; Wang, Xing ; Gao, Zijie ; Zhan, Mingtao ; Tang, Xiyuan ; Hsu, Chen-Kai ; Sun, Nan</creatorcontrib><description><![CDATA[Noise-shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) using passive loop filters have drawn the increasing attentions owing to their simplicity, low power, zero static current, and PVT robustness. However, prior works show the limited resolution because of two main challenges: the thermal noise and the digital-to-analog converter (DAC) mismatch. This article presents a high-resolution full passive NS SAR ADC. It uses an efficient NS filter architecture that realizes a 4<inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> passive gain and the passive summation, significantly reducing the total thermal noise. It also realizes the second-order DAC mismatch error shaping (MES) that is tone-free. A digital prediction is proposed to solve the signal-range loss issue caused by the MES, recovering the ADC input signal range to the full swing. A prototype NS SAR ADC is implemented in 40-nm CMOS process. It measures 90.5-dB signal-to-noise-and-distortion ratio (SNDR) and 94.3-dB dynamic range (DR) over 40-kHz bandwidth without any calibration. It consumes 67.4 <inline-formula> <tex-math notation="LaTeX">\mu \text{W} </tex-math></inline-formula> power from a 1.1-V supply and occupies 0.061 mm 2 area.]]></description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2021.3087661</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Analog to digital conversion ; Analog to digital converters ; Analog-to-digital converter (ADC) ; Calibration ; calibration-free ; Capacitors ; CMOS ; digital prediction ; Digital to analog conversion ; Digital to analog converters ; Energy resolution ; fully passive ; mismatch error shaping (MES) ; Noise ; Noise levels ; Noise measurement ; Noise reduction ; noise-shaping (NS) ; Power consumption ; Prototypes ; Robustness ; Signal processing ; Signal resolution ; successive approximation register (SAR) ; Thermal noise</subject><ispartof>IEEE journal of solid-state circuits, 2021-11, Vol.56 (11), p.3412-3423</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2021</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c208t-96968e5a3d59b0d9bc422ab2ad7514826ea152b446b36ddaaca820fda9d0ec0b3</citedby><cites>FETCH-LOGICAL-c208t-96968e5a3d59b0d9bc422ab2ad7514826ea152b446b36ddaaca820fda9d0ec0b3</cites><orcidid>0000-0003-2181-9042 ; 0000-0001-9204-3988 ; 0000-0002-5155-8405</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9459709$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,27924,27925,54796</link.rule.ids></links><search><creatorcontrib>Liu, Jiaxin</creatorcontrib><creatorcontrib>Wang, Xing</creatorcontrib><creatorcontrib>Gao, Zijie</creatorcontrib><creatorcontrib>Zhan, Mingtao</creatorcontrib><creatorcontrib>Tang, Xiyuan</creatorcontrib><creatorcontrib>Hsu, Chen-Kai</creatorcontrib><creatorcontrib>Sun, Nan</creatorcontrib><title>A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description><![CDATA[Noise-shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) using passive loop filters have drawn the increasing attentions owing to their simplicity, low power, zero static current, and PVT robustness. However, prior works show the limited resolution because of two main challenges: the thermal noise and the digital-to-analog converter (DAC) mismatch. This article presents a high-resolution full passive NS SAR ADC. It uses an efficient NS filter architecture that realizes a 4<inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> passive gain and the passive summation, significantly reducing the total thermal noise. It also realizes the second-order DAC mismatch error shaping (MES) that is tone-free. A digital prediction is proposed to solve the signal-range loss issue caused by the MES, recovering the ADC input signal range to the full swing. A prototype NS SAR ADC is implemented in 40-nm CMOS process. It measures 90.5-dB signal-to-noise-and-distortion ratio (SNDR) and 94.3-dB dynamic range (DR) over 40-kHz bandwidth without any calibration. It consumes 67.4 <inline-formula> <tex-math notation="LaTeX">\mu \text{W} </tex-math></inline-formula> power from a 1.1-V supply and occupies 0.061 mm 2 area.]]></description><subject>Analog to digital conversion</subject><subject>Analog to digital converters</subject><subject>Analog-to-digital converter (ADC)</subject><subject>Calibration</subject><subject>calibration-free</subject><subject>Capacitors</subject><subject>CMOS</subject><subject>digital prediction</subject><subject>Digital to analog conversion</subject><subject>Digital to analog converters</subject><subject>Energy resolution</subject><subject>fully passive</subject><subject>mismatch error shaping (MES)</subject><subject>Noise</subject><subject>Noise levels</subject><subject>Noise measurement</subject><subject>Noise reduction</subject><subject>noise-shaping (NS)</subject><subject>Power consumption</subject><subject>Prototypes</subject><subject>Robustness</subject><subject>Signal processing</subject><subject>Signal resolution</subject><subject>successive approximation register (SAR)</subject><subject>Thermal noise</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2021</creationdate><recordtype>article</recordtype><recordid>eNo9kMtOwzAQRS0EEqXwAYiNJdYuYydO7GVIWx4qDxEQ7KJJ7FKjkhQ7RWLNR_BB_BitWrEaXencO9Ih5JjDgHPQZ9dFkQ8ECD6IQKVJwndIj0upGE-jl13SA-CKaQGwTw5CeFvFOFa8R74zqoGZc1bcDh9ojnNXeexc27Cxt5aOl_P5F73HENynpbetC5YVM1y45pUW2QPNhjl9dt2Mxr8__9gFuoZiY2hh67Yx7M4b6-kwy-mNC-_Y1TM68r71dLt0SPamOA_2aHv75Gk8eswv2eTu4irPJqwWoDqmE50oKzEyUldgdFXHQmAl0KSSx0okFrkUVRwnVZQYg1ijEjA1qA3YGqqoT043uwvffixt6Mq3dumb1ctSSJVIDUqlK4pvqNq3IXg7LRfevaP_KjmUa9fl2nW5dl1uXa86J5uOs9b-8zqWOgUd_QHSbnlP</recordid><startdate>20211101</startdate><enddate>20211101</enddate><creator>Liu, Jiaxin</creator><creator>Wang, Xing</creator><creator>Gao, Zijie</creator><creator>Zhan, Mingtao</creator><creator>Tang, Xiyuan</creator><creator>Hsu, Chen-Kai</creator><creator>Sun, Nan</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0003-2181-9042</orcidid><orcidid>https://orcid.org/0000-0001-9204-3988</orcidid><orcidid>https://orcid.org/0000-0002-5155-8405</orcidid></search><sort><creationdate>20211101</creationdate><title>A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping</title><author>Liu, Jiaxin ; Wang, Xing ; Gao, Zijie ; Zhan, Mingtao ; Tang, Xiyuan ; Hsu, Chen-Kai ; Sun, Nan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c208t-96968e5a3d59b0d9bc422ab2ad7514826ea152b446b36ddaaca820fda9d0ec0b3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2021</creationdate><topic>Analog to digital conversion</topic><topic>Analog to digital converters</topic><topic>Analog-to-digital converter (ADC)</topic><topic>Calibration</topic><topic>calibration-free</topic><topic>Capacitors</topic><topic>CMOS</topic><topic>digital prediction</topic><topic>Digital to analog conversion</topic><topic>Digital to analog converters</topic><topic>Energy resolution</topic><topic>fully passive</topic><topic>mismatch error shaping (MES)</topic><topic>Noise</topic><topic>Noise levels</topic><topic>Noise measurement</topic><topic>Noise reduction</topic><topic>noise-shaping (NS)</topic><topic>Power consumption</topic><topic>Prototypes</topic><topic>Robustness</topic><topic>Signal processing</topic><topic>Signal resolution</topic><topic>successive approximation register (SAR)</topic><topic>Thermal noise</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Liu, Jiaxin</creatorcontrib><creatorcontrib>Wang, Xing</creatorcontrib><creatorcontrib>Gao, Zijie</creatorcontrib><creatorcontrib>Zhan, Mingtao</creatorcontrib><creatorcontrib>Tang, Xiyuan</creatorcontrib><creatorcontrib>Hsu, Chen-Kai</creatorcontrib><creatorcontrib>Sun, Nan</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Xplore (Online service)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Liu, Jiaxin</au><au>Wang, Xing</au><au>Gao, Zijie</au><au>Zhan, Mingtao</au><au>Tang, Xiyuan</au><au>Hsu, Chen-Kai</au><au>Sun, Nan</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2021-11-01</date><risdate>2021</risdate><volume>56</volume><issue>11</issue><spage>3412</spage><epage>3423</epage><pages>3412-3423</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract><![CDATA[Noise-shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) using passive loop filters have drawn the increasing attentions owing to their simplicity, low power, zero static current, and PVT robustness. However, prior works show the limited resolution because of two main challenges: the thermal noise and the digital-to-analog converter (DAC) mismatch. This article presents a high-resolution full passive NS SAR ADC. It uses an efficient NS filter architecture that realizes a 4<inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> passive gain and the passive summation, significantly reducing the total thermal noise. It also realizes the second-order DAC mismatch error shaping (MES) that is tone-free. A digital prediction is proposed to solve the signal-range loss issue caused by the MES, recovering the ADC input signal range to the full swing. A prototype NS SAR ADC is implemented in 40-nm CMOS process. It measures 90.5-dB signal-to-noise-and-distortion ratio (SNDR) and 94.3-dB dynamic range (DR) over 40-kHz bandwidth without any calibration. It consumes 67.4 <inline-formula> <tex-math notation="LaTeX">\mu \text{W} </tex-math></inline-formula> power from a 1.1-V supply and occupies 0.061 mm 2 area.]]></abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/JSSC.2021.3087661</doi><tpages>12</tpages><orcidid>https://orcid.org/0000-0003-2181-9042</orcidid><orcidid>https://orcid.org/0000-0001-9204-3988</orcidid><orcidid>https://orcid.org/0000-0002-5155-8405</orcidid></addata></record> |
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subjects | Analog to digital conversion Analog to digital converters Analog-to-digital converter (ADC) Calibration calibration-free Capacitors CMOS digital prediction Digital to analog conversion Digital to analog converters Energy resolution fully passive mismatch error shaping (MES) Noise Noise levels Noise measurement Noise reduction noise-shaping (NS) Power consumption Prototypes Robustness Signal processing Signal resolution successive approximation register (SAR) Thermal noise |
title | A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping |
url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-28T20%3A23%3A13IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%2090-dB-SNDR%20Calibration-Free%20Fully%20Passive%20Noise-Shaping%20SAR%20ADC%20With%204%C3%97%20Passive%20Gain%20and%20Second-Order%20DAC%20Mismatch%20Error%20Shaping&rft.jtitle=IEEE%20journal%20of%20solid-state%20circuits&rft.au=Liu,%20Jiaxin&rft.date=2021-11-01&rft.volume=56&rft.issue=11&rft.spage=3412&rft.epage=3423&rft.pages=3412-3423&rft.issn=0018-9200&rft.eissn=1558-173X&rft.coden=IJSCBC&rft_id=info:doi/10.1109/JSSC.2021.3087661&rft_dat=%3Cproquest_cross%3E2586590887%3C/proquest_cross%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c208t-96968e5a3d59b0d9bc422ab2ad7514826ea152b446b36ddaaca820fda9d0ec0b3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=2586590887&rft_id=info:pmid/&rft_ieee_id=9459709&rfr_iscdi=true |