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A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping

Noise-shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) using passive loop filters have drawn the increasing attentions owing to their simplicity, low power, zero static current, and PVT robustness. However, prior works show the limited resolution because of tw...

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Published in:IEEE journal of solid-state circuits 2021-11, Vol.56 (11), p.3412-3423
Main Authors: Liu, Jiaxin, Wang, Xing, Gao, Zijie, Zhan, Mingtao, Tang, Xiyuan, Hsu, Chen-Kai, Sun, Nan
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cited_by cdi_FETCH-LOGICAL-c208t-96968e5a3d59b0d9bc422ab2ad7514826ea152b446b36ddaaca820fda9d0ec0b3
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container_issue 11
container_start_page 3412
container_title IEEE journal of solid-state circuits
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creator Liu, Jiaxin
Wang, Xing
Gao, Zijie
Zhan, Mingtao
Tang, Xiyuan
Hsu, Chen-Kai
Sun, Nan
description Noise-shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) using passive loop filters have drawn the increasing attentions owing to their simplicity, low power, zero static current, and PVT robustness. However, prior works show the limited resolution because of two main challenges: the thermal noise and the digital-to-analog converter (DAC) mismatch. This article presents a high-resolution full passive NS SAR ADC. It uses an efficient NS filter architecture that realizes a 4 \times passive gain and the passive summation, significantly reducing the total thermal noise. It also realizes the second-order DAC mismatch error shaping (MES) that is tone-free. A digital prediction is proposed to solve the signal-range loss issue caused by the MES, recovering the ADC input signal range to the full swing. A prototype NS SAR ADC is implemented in 40-nm CMOS process. It measures 90.5-dB signal-to-noise-and-distortion ratio (SNDR) and 94.3-dB dynamic range (DR) over 40-kHz bandwidth without any calibration. It consumes 67.4 \mu \text{W} power from a 1.1-V supply and occupies 0.061 mm 2 area.
doi_str_mv 10.1109/JSSC.2021.3087661
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ispartof IEEE journal of solid-state circuits, 2021-11, Vol.56 (11), p.3412-3423
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source IEEE Xplore (Online service)
subjects Analog to digital conversion
Analog to digital converters
Analog-to-digital converter (ADC)
Calibration
calibration-free
Capacitors
CMOS
digital prediction
Digital to analog conversion
Digital to analog converters
Energy resolution
fully passive
mismatch error shaping (MES)
Noise
Noise levels
Noise measurement
Noise reduction
noise-shaping (NS)
Power consumption
Prototypes
Robustness
Signal processing
Signal resolution
successive approximation register (SAR)
Thermal noise
title A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping
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