Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology

In this article, we present an energy-efficient high bandwidth array design using 0.0300- \mu \text{m}^{2} high-performance SRAM bitcell on Intel 4 CMOS technology. By employing a unique combination of design techniques-column mux (CM) of 1, flying BL (FBL), passive write assist scheme, and energy-...

Full description

Saved in:
Bibliographic Details
Published in:IEEE journal of solid-state circuits 2023-04, Vol.58 (4), p.1087-1093
Main Authors: Kim, Yusung, Ong, Clifford, Pillai, Anandkumar Mahadevan, Jagadeesh, Harish, Baek, Gwanghyeon, Rajwani, Iqbal, Guo, Zheng, Karl, Eric
Format: Article
Language:English
Subjects:
Bandwidth
Circuit stability
CMOS integrated circuits
CMOS technology
Computer architecture
Microprocessors
Random access memory
read energy
semiconductor memory
Static random access memory
static random access memory (SRAM)
Transistors
write energy
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:In this article, we present an energy-efficient high bandwidth array design using 0.0300- \mu \text{m}^{2} high-performance SRAM bitcell on Intel 4 CMOS technology. By employing a unique combination of design techniques-column mux (CM) of 1, flying BL (FBL), passive write assist scheme, and energy-efficient column design-the proposed 6T SRAM array design demonstrates >80% access energy improvement over a conventional four-way interleaved 6T SRAM array design and 30% macro density improvement compared to a hierarchical bitline (BL) 8T SRAM design for high bandwidth memory applications.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2022.3230046