A 112-Gb/s Serial Link Transceiver With Three-Tap FFE and 18-Tap DFE Receiver for up to 43-dB Insertion Loss Channel in 7-nm FinFET Technology

This article presents a power- and area-efficient multistandard serial link transceiver designed for application rates of up to 112 Gb/s, such as OIF CEI-112G and IEEE 802.3ck 400GBASE. The receiver features a continuous time linear equalizer, a programmable gain amplifier (PGA), a three-tap samplin...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2024-01, Vol.59 (1), p.8-18
Main Authors: Zhang, Bo, Vasani, Anand, Sinha, Ashutosh, Nilchi, Alireza, Tong, Haitao, Rao, Lakshmi P., Khanoyan, Karapet, Hatamkhani, Hamid, Yang, Xiaochen, Meng, Xin, Wong, Alexander, Kim, Jun, Jing, Ping, Sun, Yehui, Nazemi, Ali, Liu, Dean, Brewster, Anthony, Cao, Jun, Momtaz, Afshin
Format: Article
Language:English
Subjects:
1 + D pulse shaping
112G
7-bit digital to analog converter (DAC)
Amplification
backplane
Clocks
data center
decision feedback equalizer (DFE)
Decision feedback equalizers
Digital to analog converters
Equalizers
feed-forward equalizer (FFE)
forward error correction (FEC)
Insertion loss
look ahead
NRZ
PAM4
Phase locked loops
Pulse shaping methods
quarter-rate topology
Receivers
serial link transceiver
source-series terminated (SST) driver
Transceivers
Transmitters
Vibration
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Summary:This article presents a power- and area-efficient multistandard serial link transceiver designed for application rates of up to 112 Gb/s, such as OIF CEI-112G and IEEE 802.3ck 400GBASE. The receiver features a continuous time linear equalizer, a programmable gain amplifier (PGA), a three-tap sampling-based feed-forward equalizer, and an 18-tap decision feedback equalizer. The transmitter uses a half-rate 2:1 multiplexer (MUX) with a duty cycle distortion corrected clock and a 7-bit digital to analog converter (DAC)-based driver with a six-tap feed-forward equalizer. The shared phase-locked loop (PLL) has a tuning range of 40-60 GHz with 0.12-ps rms jitter in integer mode and 0.16-ps jitter in fractional- {N} mode measured at 56 GHz. The transmitter shows an eye with an RLM of 0.999. The transceiver can compensate for up to 43.9-dB insertion loss (IL) channel at 112 Gb/s. It consumes 690-mW per receiver (RX)/transmitter (TX). It is fabricated in 7-nm FinFET technology and occupies 0.63-mm2 per RX/TX.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2023.3313524