A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC

• Published in: IEEE journal of solid-state circuits 2024-08, Vol.59 (8), p.2481-2491
• Main Authors: Chung, Jae-Hyun, Kim, Ye-Dam, Park, Chang-Un, Park, Kun-Woo, Oh, Dong-Ryeol, Seo, Min-Jae, Ryu, Seung-Tak
• Format: Article
• Language: English
• Subjects: Amplification; Amplifier design; Amplifiers; Analog to digital converters; Analog-to-digital converter (ADC); capacitive interpolation; Digital to analog converters; Figure of merit; Gain; high-resolution dual-residue (D-R) pipelined-successive approximation register (SAR) analog-to-digital converter (ADC); inter-stage gain error; Interpolation; kT/C noise cancellation; Noise levels; noise shaping (NS); Parasitics (electronics); Pipelines; Quantization (signal); quantization leakage error; Redundancy; Residues; SAR-ADC; segmented digital-to-analog converter (DAC); Signal resolution; Timing
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2024.3360944

This article presents an energy-efficient high-resolution dual-residue (D-R) pipelined-successive approximation register (SAR) analog-to-digital converter (ADC), with a backend capacitive interpolating SAR ADC incorporated with noise-shaping (NS) capability. The residue amplifier design could be simplified as the residue is pre-amplified by the amplifier for the kT/ C -noise cancellation. Moreover, the proposed segmented digital-to-analog converter (DAC) structure overcomes parasitic capacitance limitations in the capacitive interpolation, improving resolution along with the gain-error-free advantage of the D-R structure. Fabricated in a 180-nm CMOS technology, the prototype ADC achieves an 81.2-dB signal-to-noise and distortion ratio (SNDR) and an 89.9-dB spurious-free dynamic range (SFDR) in a 1.5-MHz bandwidth (BW) at an over-sampling ratio (OSR) of 8 with a 170.4-dB SNDR Schreier figure-of-merit (FoM) without any calibration.