A High-Resolution Pipelined-SAR ADC Using Cyclically Charged Floating Inverter Amplifier

• Published in: IEEE journal of solid-state circuits 2024-10, Vol.59 (10), p.3242-3252
• Main Authors: Park, Changjoo, Kim, Jeongmyeong, Kang, Kyounghun, Yang, Minkyu, Moon, Byeongmin, Lee, Siheon, Jung, Wanyeong
• Format: Article
• Language: English
• Subjects: ADC; Amplifiers; Bias; Capacitance; Capacitors; Charge efficiency; Closed loops; Current efficiency; Energy efficiency; energy-efficient ADC; Figure of merit; floating inverter amplifier (FIA); Inverters; pipelined-SAR ADC; Reconfiguration; Reservoirs; residue amplifier; Sampling; Switches; Voltage
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2024.3419759

This article presents an energy-efficient and easily adjustable floating-inverter amplifier (FIA), named the cyclically charged FIA (CC-FIA). Its bias point can be adjusted to a stable operating region by reusing multiple switched capacitors, which allows for enhancing current efficiency ( g_{m}/I_{D} ) by setting its bias point in the near- or sub-threshold region. Easy reconfiguration of bias points enables maximizing amplifier energy efficiency across different sampling frequencies for event-driven ADC. The proposed FIA also features a stable and easily tuned open-loop gain, eliminating stability issues in closed-loop configurations and further enhancing its energy efficiency. It occupies a significantly smaller area than conventional FIAs because each reservoir capacitor pumps charge to the amplifier multiple times. The CC-FIA is implemented in a pipelined-SAR ADC as an open-loop residue amplifier and fabricated in a 65-nm CMOS process. The prototype ADC achieves an SNDR of 74.0 dB and an SFDR of 85.5 dB at a sampling frequency of 2 MS/s. The ADC consumes 72.3~{\mu } W at a supply voltage of 1.2 V, resulting in a Schreier figure-of-merit of 175.4 dB.