A 16-Gb 37-Gb/s GDDR7 DRAM With PAM3-Optimized TRX Equalization and ZQ Calibration

The development of the graphics double-data-rate 7 (GDDR7) dynamic random access memory (DRAM) standard aims to overcome the constraints of its predecessor, GDDR6, in order to achieve higher speed operation. This article introduces a 16-Gb GDDR7 DRAM with three-level pulse amplitude modulation (PAM3...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2024-10, p.1-13
Main Authors: Cho, Sung-Yong, Choi, Moon-Chul, Baek, Jaehyeok, An, Donggun, Kim, Sang-Hoon, Lee, Daewoong, Yang, Seongyeal, Kim, Se-Mi, Kang, Gil-Young, Park, Juseop, Lee, Kyung-Ho, Jung, Hwan-Chul, Cho, Gun-Hee, Lee, Chan-Yong, Kim, Hye-Ran, Shin, Yong-Jae, Park, Hanna, Lee, Sang-Yong, Kim, Jonghyuk, Won, Bokyeon, Mok, Jungil, Kim, Kijin, Lim, Un-Hak, Jin, Hongjun, Lee, YoungSeok, Kim, Young-Tae, Ha, Heonjoo, Ahn, Jinchan, Sung, Won Ju, Jang, Yoontaek, Song, Hoyoung, Ban, Hyodong, Park, Tae-Hoon, Yoo, Changsik, Oh, Tae-Young, Hwang, SangJoon
Format: Article
Language:English
Subjects:
Bandwidth
Calibration
Clocks
Codes
Decision feedback equalizer (DFE)
Encoding
graphic double data rate (GDDR)
high-speed memory
Jitter
Pins
Power demand
Random access memory
single ended
Symbols
three-level pulse amplitude modulation (PAM3)
wireline transceiver
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Summary:The development of the graphics double-data-rate 7 (GDDR7) dynamic random access memory (DRAM) standard aims to overcome the constraints of its predecessor, GDDR6, in order to achieve higher speed operation. This article introduces a 16-Gb GDDR7 DRAM with three-level pulse amplitude modulation (PAM3) interface in a DRAM process. The proposed GDDR7 consists of two dies/four channels to support both two-and four-channel mode configuration. An adaptive gain-controlled feedforward equalizer (FFE) is implemented in the transmitter (TX) and data-dependent separately gain-controlled one-tap decision feedback equalizer (DFE) is proposed in the receiver (RX). In addition, the proposed ZQ calibration scheme uses alternately switched reference voltages to enhance the level mismatch ratio (RLM) of the PAM3 signaling. Moreover, low-power and low-jitter clocking techniques with a low-dropout (LDO) regulator and CMOS distribution are employed for WCK distribution; thereby, 60 mA per die of current reduction and 0.16 ps/mV of power-supply-induced jitter (PSIJ) could be achieved. The proposed GDDR7 achieves 37 Gb/s at 1.2 V and 32 Gb/s at 1.1 V with a 1z-nm DRAM technology.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2024.3472463