A Sub-0.8-pJ/bit Universal Soft-Detection Decoder Using ORBGRAND

Guessing random additive noise decoding (GRAND) has enabled the practical implementation of maximum likelihood (ML) or near-ML decoding, shifting the paradigm of code-specific decoder design to a code-agnostic decoding architecture. Ordered reliability bits GRAND (ORBGRAND) is a soft-detection varia...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2024-11, p.1-15
Main Authors: Riaz, Arslan, Yasar, Alperen, Ercan, Furkan, An, Wei, Ngo, Jonathan, Galligan, Kevin, Medard, Muriel, Duffy, Ken R., Yazicigil, Rabia Tugce
Format: Article
Language:English
Subjects:
Additive noise
Codes
Decoder
Energy efficiency
forward error correction
guessing random additive noise decoding (GRAND)
Hardware
Iterative decoding
Maximum likelihood decoding
Noise
ordered reliability bits GRAND (ORBGRAND)
Power demand
Reliability
soft detection
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Summary:Guessing random additive noise decoding (GRAND) has enabled the practical implementation of maximum likelihood (ML) or near-ML decoding, shifting the paradigm of code-specific decoder design to a code-agnostic decoding architecture. Ordered reliability bits GRAND (ORBGRAND) is a soft-detection variant of GRAND that uses soft information to guide its query order to significantly improve the decoding performance. This work presents the first-integrated energy-efficient hardware implementation of ORBGRAND to achieve ultra-low energy (sub-pJ/bit) and power consumption (5 mW) while using a small core area of 0.4 mm 2 in 40-nm CMOS. The proposed architecture enables dynamic power savings by implementing an efficient sorter that allows the decoder to use the sorted bits immediately without waiting for the entire list to be sorted and an efficient landslide unit that generates noise effect sequences in parallel. The chip is implemented in 40-nm CMOS with a re-configurable architecture that enables decoding of any binary linear code from 32 to 256 bits of code length and 0.8-1 code rate. For a code length of 256 bits and a code rate of 0.94, it provides a measured energy consumption of 0.76 pJ/bit and power consumption of 4.9 mW from a 1.0-V supply voltage at an operating frequency of 90 MHz providing a throughput of 6.5 Gb/s and a latency of 40 ns at a targeted frame error rate (FER) of 10 -7 .
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2024.3502240