Performance Optimization and Improvement of Silicon Avalanche Photodetectors in Standard CMOS Technology

This paper discusses design optimization for silicon avalanche photodetectors (APDs) fabricated in standard complementary metal-oxide-semiconductor (CMOS) technology in order to achieve the highest possible performance. Such factors as PN junctions, guard ring structures, active areas, and back-end...

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Bibliographic Details
Published in:IEEE journal of selected topics in quantum electronics 2018-03, Vol.24 (2), p.1-13
Main Authors: Lee, Myung-Jae, Choi, Woo-Young
Format: Article
Language:English
Subjects:
Avalanche photodetector (APD)
avalanche photodiode
Bandwidth
carrier acceleration
CMOS technology
edge breakdown
equivalent circuit model
Equivalent circuits
guard ring
image sensor
inductive peaking
Integrated circuit modeling
Junctions
multiple junction
optical detector
optical interconnect
photodetection bandwidth
photodetector
photodiode
Silicon
silicon photonics
spatially-modulated avalanche photodetector
standard CMOS technology
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Summary:This paper discusses design optimization for silicon avalanche photodetectors (APDs) fabricated in standard complementary metal-oxide-semiconductor (CMOS) technology in order to achieve the highest possible performance. Such factors as PN junctions, guard ring structures, active areas, and back-end structures are considered for the optimization. CMOS-APDs reflecting varying aspects of these factors are fabricated and their performances are characterized. In addition, their characteristics are analyzed with technology computer-aided-design simulations and equivalent circuit models. From these investigations, dominant factors that influence the CMOS-APD performance are identified. Furthermore, three different techniques enabling further performance improvements of CMOS-APDs are investigated, which are spatial-modulation, carrier-acceleration, and multijunction techniques. The state-of-the-art CMOS-APDs' structures and performances are presented and compared, and the best optimized CMOS-APD is proposed. These results should be extremely useful for realizing optimal silicon APDs in standard CMOS technology for various applications.
ISSN:1077-260X
1558-4542
DOI:10.1109/JSTQE.2017.2754359