hbox^/\hbox^ Gate Bulk FinFETs With Locally Separated Channel Structure for Sub-50-nm DRAM Cell Transistors

• Published in: IEEE electron device letters 2007-12, Vol.28 (12), p.1126-1128
• Main Authors: Jung, Han-A-Reum, Park, Ki-Heung, Lee, Jong-Ho
• Format: Article
• Language: English
• Subjects: Business; Channel separation; DRAM chips; dynamic random access memory (DRAM); Electronic mail; Etching; FETs; Filling; fin-type field-effect transistor (FinFET); FinFETs; gate-induced drain leakage (GIDL); hbox{n}^{+}/\hbox{p}^{+} gate; Nonvolatile memory; Random access memory; sub-50 nm; Threshold voltage
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2007.909870

We proposed a new p + /n + poly-Si gate bulk fin-type field-effect transistor that has two channel fins separated locally by a shallow trench filled with oxide or p + polygate. Key device characteristics were investigated by changing the n + poly-Si gate length La, the material filling the trench, and the width and length of the trench at a given gate length L g . It was shown that the trench filled with p + poly-Si gate should not be contacted with the source/drain diffusion region to achieve an excellent I on /I off (> 1010) that is suitable for sub-50-nm dynamic random access memory cell transistors. Based on the aforementioned device structure, we designed reasonable Ls/Lg and channel fin width W cfin at given L g 's of 30, 40, and 50 nm.