Effect of a Two-Step Recess Process Using Atomic Layer Etching on the Performance of \hbox\hbox\hbox\hbox\hbox p-HEMTs

• Published in: IEEE electron device letters 2007-12, Vol.28 (12), p.1086-1088
• Main Authors: Kim, Tae-Woo, Kim, Dae-Hyun, Park, Sang Duk, Yeom, Geun Young, Lim, Byeong Ok, Rhee, Jin-Koo, Jang, Jae-Hyung, Song, Jong-In
• Format: Article
• Language: English
• Subjects: Artificial intelligence; Atomic layer deposition; Atomic layer etching (ALET); drain-induced barrier lowering (DIBL); Etching; HEMTs; I_{\rm ON}/I_{\rm OFF} ratio; Indium compounds; Indium gallium arsenide; MODFETs; PHEMTs; Plasma applications; Plasma properties; pseudomorphic high-electron mobility transistor (p-HEMT); subthreshold slope
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2007.910278

The characteristics of 0.15- mum InAlAs/InGaAs pseudomorphic high-electron mobility transistors (p-HEMTs) that were fabricated using the Ne-based atomic layer etching (ALET) technology and the Ar-based conventional reactive ion etching (RIE) technology were investigated. As compared with the RIE, the ALET used a much lower plasma energy and thus produced much lower plasma-induced damages to the surface and bulk of the In 0.52 AI 0.48 As barrier and showed a much higher etch selectivity (~70) of the InP spacer against the In 0.52 Al 0.48 As barrier. The 0.15-mum InAlAs/InGaAs p-HEMTs that were fabricated using the ALET exhibited improved G m,max (1.38 S/mm), I ON n/I OFF (1.18X10 4 ), drain-induced barrier lowering (80 mWV), threshold voltage uniformity (V th,avg = -190 mV and alpha = 15 mV), and ftau (233 GHz), mainly due to the extremely low plasma-induced damage in the Schottky gate area.