Performance Comparison Between Bulk and SOI Junctionless Transistors

• Published in: IEEE electron device letters 2013-02, Vol.34 (2), p.169-171
• Main Authors: HAN, Ming-Hung, CHANG, Chun-Yen, CHEN, Hung-Bin, WU, Jia-Jiun, CHENG, Ya-Chi, WU, Yung-Chun
• Format: Article
• Language: English
• Subjects: 3-D simulation; Applied sciences; Doping; Electronics; Exact sciences and technology; Fin-shaped field-effect transistor (FinFET); FinFETs; junctionless (JL); Logic gates; Mathematical model; Molecular electronics, nanoelectronics; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductor process modeling; Substrates; Transistors
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2012.2231395

The design and characteristics of a junctionless (JL) bulk FinFET were compared with the silicon-on-insulator (SOI) JL nanowire transistor (JNT) using 3-D quantum transport device simulation. The JL bulk FinFET exhibits a favorable on/offcurrent ratio and short-channel characteristics by reducing the effective channel thickness that is caused by the channel/substrate junction. The drain-induced barrier lowering and the subthreshold slope are about 40 mV and 73 mV/dec, respectively, with an on/offcurrent ratio of 10 5 at W = 10 nm. The JL bulk FinFET is less sensitive to the channel thickness than the SOI JNT. Furthermore, the threshold voltage V th of the JL bulk FinFET can be easily tuned by varying substrate doping concentration N sub . The modulation range of V th as N sub changes from 10 18 to 10 19 cm -3 , which is around 30%.