A Traveling-Wave CMOS SPDT Using Slow-Wave Transmission Lines for Millimeter-Wave Application

• Published in: IEEE electron device letters 2013-09, Vol.34 (9), p.1094-1096
• Main Authors: Xiao-Lan Tang, Pistono, Emmanuel, Ferrari, Philippe, Fournier, Jean-Michel
• Format: Article
• Language: English
• Subjects: 65-nm RF-CMOS process; Applied sciences; Circuit properties; CMOS integrated circuits; Design. Technologies. Operation analysis. Testing; Electric, optical and optoelectronic circuits; Electronic circuits; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; Engineering Sciences; Exact sciences and technology; Insertion loss; Integrated circuits; Loss measurement; Micro and nanotechnologies; Microelectronics; Millimeter wave technology; millimeter-wave; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; single-pole double-throw (SPDT); slow-wave coplanar waveguide; Switches; Switching circuits; Switching, multiplexing, switched capacity circuits; Transistors; Transmission line measurements; traveling-wave; triple-well MOS
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2013.2274452

In this letter, a traveling-wave single-pole double-throw (SPDT) switch using slow-wave coplanar waveguides is implemented in a 65-nm triple-well CMOS process. For performance improvement, double-well body-floating technique is used. The p-well layer and deep n-well layer of nMOSFET being, respectively, biased to -1.4 and 2.0 V, the measured SPDT exhibits an insertion loss of 2.8 dB and an isolation of 20 dB at 60 GHz. A measured input 1-dB compression point (ICP1dB) of 17 dBm is obtained at 35 GHz (16.3 dBm at 60 GHz by simulation). The total chip size is only 0.42 mm 2 (780 μm× 540 μm) including all testing pads.