Optimization of Bias Schemes for Long-Term Endurable 1T-DRAM Through the Use of the Biristor Mode Operation

• Published in: IEEE electron device letters 2014-02, Vol.35 (2), p.220-222
• Main Authors: KIM, Dong-Oh, MOON, Dong-Il, CHOI, Yang-Kyu
• Format: Article
• Language: English
• Subjects: 1T-DRAM mode; Applied sciences; biristor; biristor mode; Bistable resistor; Boron; capacitorless one-transistor DRAM; Degradation; Design. Technologies. Operation analysis. Testing; disturbance; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; endurance; Exact sciences and technology; Hot carriers; Integrated circuits; Integrated circuits by function (including memories and processors); Logic gates; Programming; Random access memory; Resistors; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Transistors
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2013.2295240

The long-term endurance characteristics are investigated for MOSFET-based capacitorless one-transistor DRAM (1T-DRAM) under the conventional versus biristor mode. Based on the experimental results and on a supporting simulation study, it was found that the MOSFET-based 1T-DRAM, when enabled by a biristor mode, is preferred for long-term endurance compared with MOSFET-based 1T-DRAM when operated in a conventional mode. Although a high drain voltage is required in the biristor mode for programming, improved endurance characteristics are observed. The simulation study showed that this feature is achieved by the suppression of hot-hole-induced degradation, which arises from the absence of a gate use at the dynamic cell. Thus, this letter provides a new type of device architecture as well as a novel and innovative operational method pertaining to conventional 1T-DRAM to mitigate the problem of limited endurance.