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Tunable Stability of All-Inkjet-Printed Double-Gate Carbon Nanotube Thin Film Transistors
In this letter, we improved the stability of all-inkjet-printed carbon nanotube thin film transistors (CNT TFTs) by employing a double gate (DG) structure under an optimal bias condition. In the single-gate structure, the positive threshold voltage (VTH) shift under 10 V positive gate bias stress (P...
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Published in: | IEEE electron device letters 2020-06, Vol.41 (6), p.860-863 |
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creator | Yoo, Hyunjun Ha, Jewook Kim, Hyeonggyu Seo, Jiseok Lee, Soo-Yeon Hong, Yongtaek |
description | In this letter, we improved the stability of all-inkjet-printed carbon nanotube thin film transistors (CNT TFTs) by employing a double gate (DG) structure under an optimal bias condition. In the single-gate structure, the positive threshold voltage (VTH) shift under 10 V positive gate bias stress (PGBS) was significantly reduced with poly(4-vinylphenol) passivation. However, after 100 s, the on-current level was decreased, and a large negative VTH shift was observed. We adopted DG CNT TFTs for a further improvement. When -3 V was applied to the top gate, the DG CNT TFTs not only exhibited a much lower VTH shift but also showed a stabilized on-current level. When an appropriate bias is applied to the top gate, charge trapping is induced at the top gate interface and it might balance between the positive and negative shifts. As a result, the overall stress effect is reduced. The p-type only inverter adopting a DG CNT TFT showed improved stability under -3 V of top gate bias. Our experimental result shows that DG structure is a promising candidate for various CNT circuit designs. |
doi_str_mv | 10.1109/LED.2020.2990701 |
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In the single-gate structure, the positive threshold voltage (VTH) shift under 10 V positive gate bias stress (PGBS) was significantly reduced with poly(4-vinylphenol) passivation. However, after 100 s, the on-current level was decreased, and a large negative VTH shift was observed. We adopted DG CNT TFTs for a further improvement. When -3 V was applied to the top gate, the DG CNT TFTs not only exhibited a much lower VTH shift but also showed a stabilized on-current level. When an appropriate bias is applied to the top gate, charge trapping is induced at the top gate interface and it might balance between the positive and negative shifts. As a result, the overall stress effect is reduced. The p-type only inverter adopting a DG CNT TFT showed improved stability under -3 V of top gate bias. Our experimental result shows that DG structure is a promising candidate for various CNT circuit designs.</description><identifier>ISSN: 0741-3106</identifier><identifier>EISSN: 1558-0563</identifier><identifier>DOI: 10.1109/LED.2020.2990701</identifier><identifier>CODEN: EDLEDZ</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Bias ; Carbon nanotubes ; Circuit design ; Circuit stability ; Dielectrics ; double-gate FETs ; Inverters ; Ions ; Logic gates ; Passivation ; Semiconductor devices ; solution process ; Stability ; Stress ; Thin film transistors ; Thin films ; Threshold voltage ; Transistors</subject><ispartof>IEEE electron device letters, 2020-06, Vol.41 (6), p.860-863</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2020</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c291t-67546359ec8c509b87df2c699bde71e8c637160f755d52394355c249574960f33</citedby><cites>FETCH-LOGICAL-c291t-67546359ec8c509b87df2c699bde71e8c637160f755d52394355c249574960f33</cites><orcidid>0000-0002-7782-0758 ; 0000-0003-1030-5628 ; 0000-0001-9399-5948 ; 0000-0002-2605-6825</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9079497$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,27923,27924,54795</link.rule.ids></links><search><creatorcontrib>Yoo, Hyunjun</creatorcontrib><creatorcontrib>Ha, Jewook</creatorcontrib><creatorcontrib>Kim, Hyeonggyu</creatorcontrib><creatorcontrib>Seo, Jiseok</creatorcontrib><creatorcontrib>Lee, Soo-Yeon</creatorcontrib><creatorcontrib>Hong, Yongtaek</creatorcontrib><title>Tunable Stability of All-Inkjet-Printed Double-Gate Carbon Nanotube Thin Film Transistors</title><title>IEEE electron device letters</title><addtitle>LED</addtitle><description>In this letter, we improved the stability of all-inkjet-printed carbon nanotube thin film transistors (CNT TFTs) by employing a double gate (DG) structure under an optimal bias condition. In the single-gate structure, the positive threshold voltage (VTH) shift under 10 V positive gate bias stress (PGBS) was significantly reduced with poly(4-vinylphenol) passivation. However, after 100 s, the on-current level was decreased, and a large negative VTH shift was observed. We adopted DG CNT TFTs for a further improvement. When -3 V was applied to the top gate, the DG CNT TFTs not only exhibited a much lower VTH shift but also showed a stabilized on-current level. When an appropriate bias is applied to the top gate, charge trapping is induced at the top gate interface and it might balance between the positive and negative shifts. As a result, the overall stress effect is reduced. The p-type only inverter adopting a DG CNT TFT showed improved stability under -3 V of top gate bias. Our experimental result shows that DG structure is a promising candidate for various CNT circuit designs.</description><subject>Bias</subject><subject>Carbon nanotubes</subject><subject>Circuit design</subject><subject>Circuit stability</subject><subject>Dielectrics</subject><subject>double-gate FETs</subject><subject>Inverters</subject><subject>Ions</subject><subject>Logic gates</subject><subject>Passivation</subject><subject>Semiconductor devices</subject><subject>solution process</subject><subject>Stability</subject><subject>Stress</subject><subject>Thin film transistors</subject><subject>Thin films</subject><subject>Threshold voltage</subject><subject>Transistors</subject><issn>0741-3106</issn><issn>1558-0563</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2020</creationdate><recordtype>article</recordtype><recordid>eNo9kE1LAzEQhoMoWKt3wUvAc-rkuzmW1tZCUcH14GnJ7mYxdbtbk-yh_94tLZ4G3nneGXgQuqcwoRTM0-Z5MWHAYMKMAQ30Ao2olFMCUvFLNAItKOEU1DW6iXELQIXQYoS-sr61RePwR7KFb3w64K7Gs6Yh6_Zn6xJ5D75NrsKLrh8wsrLJ4bkNRdfiV9t2qS8czr59i5e-2eEs2Db6mLoQb9FVbZvo7s5zjD6Xz9n8hWzeVuv5bENKZmgiSkuhuDSunJYSTDHVVc1KZUxROU3dtFRcUwW1lrKSjBvBpSyZMFILM8Scj9Hj6e4-dL-9iynfdn1oh5c5E6AGFULLgYITVYYuxuDqfB_8zoZDTiE_CswHgflRYH4WOFQeThXvnPvHh50RRvM_GuNqCQ</recordid><startdate>20200601</startdate><enddate>20200601</enddate><creator>Yoo, Hyunjun</creator><creator>Ha, Jewook</creator><creator>Kim, Hyeonggyu</creator><creator>Seo, Jiseok</creator><creator>Lee, Soo-Yeon</creator><creator>Hong, Yongtaek</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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In the single-gate structure, the positive threshold voltage (VTH) shift under 10 V positive gate bias stress (PGBS) was significantly reduced with poly(4-vinylphenol) passivation. However, after 100 s, the on-current level was decreased, and a large negative VTH shift was observed. We adopted DG CNT TFTs for a further improvement. When -3 V was applied to the top gate, the DG CNT TFTs not only exhibited a much lower VTH shift but also showed a stabilized on-current level. When an appropriate bias is applied to the top gate, charge trapping is induced at the top gate interface and it might balance between the positive and negative shifts. As a result, the overall stress effect is reduced. The p-type only inverter adopting a DG CNT TFT showed improved stability under -3 V of top gate bias. Our experimental result shows that DG structure is a promising candidate for various CNT circuit designs.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/LED.2020.2990701</doi><tpages>4</tpages><orcidid>https://orcid.org/0000-0002-7782-0758</orcidid><orcidid>https://orcid.org/0000-0003-1030-5628</orcidid><orcidid>https://orcid.org/0000-0001-9399-5948</orcidid><orcidid>https://orcid.org/0000-0002-2605-6825</orcidid></addata></record> |
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subjects | Bias Carbon nanotubes Circuit design Circuit stability Dielectrics double-gate FETs Inverters Ions Logic gates Passivation Semiconductor devices solution process Stability Stress Thin film transistors Thin films Threshold voltage Transistors |
title | Tunable Stability of All-Inkjet-Printed Double-Gate Carbon Nanotube Thin Film Transistors |
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