A Hybrid Instruction Prefetching Mechanism for Ultra Low-Power Multicore Clusters

• Published in: IEEE embedded systems letters 2017-12, Vol.9 (4), p.125-128
• Main Authors: Payami, Maryam, Azarkhish, Erfan, Loi, Igor, Benini, Luca
• Format: Article
• Language: English
• Subjects: Embedded multicore processing; Energy efficiency; instruction cache; instruction prefetching; Low-power electronics; Prefetching; ultralow-power (ULP) embedded multicores
• ISSN: 1943-0663; 1943-0671
• DOI: 10.1109/LES.2017.2707978

The instruction memory hierarchy plays a critical role in performance and energy efficiency of ultralow-power (ULP) processors for the Internet-of-Things (IoT) end-nodes. This is mainly due to the extremely tight power envelope and area budgets, which imply small instruction-caches (I-Cache) operating at very low supply voltages (near-threshold). The challenge is aggravated by the fact that multiple processors, fetching in parallel, require plenty of bandwidth from the I-Caches. In this letter, we propose a low-cost and energy efficient hybrid instruction-prefetching mechanism to be integrated with a ULP multicore cluster. We study its performance for a wide range of IoT applications, from cryptography to computer vision, and show that it can effectively improve the hit-rate of almost all of them to above 95% (average performance improvement of over 2×). In addition, we designed our prefetcher and integrated it in a 4-cores cluster in 28 nm fully-depleted silicon-on-insulator (FDSOI) technology. We show that system's power consumption increases only by about 11% and silicon area by less than 1%. Altogether, a total energy reduction of 1.9× is achieved, thanks to more than 2× performance improvement, enabling a significantly longer battery life.