1.2-2.8-GHz 32.4-dBm Digital Power Amplifier With Balance-Compensated Matching Network

In this letter, a wideband watt-level digital power amplifier (DPA) with a balance-compensated matching network is proposed for polar transmitters. The balance response of the differential to the single-ended transformer is enhanced by a series-loaded compensation capacitor, which leads to the impro...

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Published in:IEEE microwave and wireless components letters 2021-01, Vol.31 (1), p.41-44
Main Authors: Wang, Tianyi, Qian, Huizhen Jenny, Yang, Bingzheng, Luo, Xun
Format: Article
Language:English
Subjects:
Balance-compensated matching network
Capacitors
CMOS
CMOS technology
digital power amplifier (DPA)
efficiency enhancement
Impedance
Matching
Power amplifiers
Power generation
Power transformers
Quadrature amplitude modulation
Transmitters
watt-level
Wideband
Wireless communication
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container_title IEEE microwave and wireless components letters
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creator Wang, Tianyi
Qian, Huizhen Jenny
Yang, Bingzheng
Luo, Xun
description In this letter, a wideband watt-level digital power amplifier (DPA) with a balance-compensated matching network is proposed for polar transmitters. The balance response of the differential to the single-ended transformer is enhanced by a series-loaded compensation capacitor, which leads to the improvement of the DPA efficiency. To verify the mechanisms, a prototype DPA is fabricated in conventional 40-nm CMOS technology. The proposed DPA operates over 1.2-2.8 GHz and exhibits a peak output power of 32.4 dBm at 2 GHz and a peak drain efficiency of 53.8% at 1.8 GHz. It supports 50-MHz 64-quadratic-amplitude modulation (QAM) with average output power ( P_{\text {avg}} ) of 25.37 dBm, error vector magnitude (EVM) of −26.97 dB, adjacent channel power ratio (ACPR) of −29.61 dBc, and 10-MHz 1024-QAM with P_{\text {avg}} of 22.14 dBm, EVM of −35.75 dB, and ACPR of −35.37 dBc, respectively.
doi_str_mv 10.1109/LMWC.2020.3035218
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The balance response of the differential to the single-ended transformer is enhanced by a series-loaded compensation capacitor, which leads to the improvement of the DPA efficiency. To verify the mechanisms, a prototype DPA is fabricated in conventional 40-nm CMOS technology. The proposed DPA operates over 1.2-2.8 GHz and exhibits a peak output power of 32.4 dBm at 2 GHz and a peak drain efficiency of 53.8% at 1.8 GHz. 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source IEEE Electronic Library (IEL) Journals
subjects Balance-compensated matching network
Capacitors
CMOS
CMOS technology
digital power amplifier (DPA)
efficiency enhancement
Impedance
Matching
Power amplifiers
Power generation
Power transformers
Quadrature amplitude modulation
Transmitters
watt-level
Wideband
Wireless communication
title 1.2-2.8-GHz 32.4-dBm Digital Power Amplifier With Balance-Compensated Matching Network
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