A 32-42-GHz RTWO-Based Frequency Quadrupler Achieving >37 dBc Harmonic Rejection in 22-nm FD-SOI

In this letter, we propose a 32-42-GHz frequency quadrupler that performs digital logic operations between four phase-shifted differential signals at one-fourth of the output frequency. The four phase-shifted signals are generated via a 10-GHz rotary traveling-wave oscillator (RTWO) and are symmetri...

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Bibliographic Details
Published in:IEEE solid-state circuits letters 2021, Vol.4, p.72-75
Main Authors: Shehata, Mohamed Atef, Roy, Vivek, Breslin, James, Shanan, Hyman, Keaveney, Michael, Staszewski, Robert Bogdan
Format: Article
Language:English
Subjects:
40 GHz
FD-SOI
Frequency measurement
frequency multiplier
frequency quadrupler
Harmonic analysis
harmonic rejection
Method of moments
millimeter-wave (mmW or mm-Wave)
multiphase
Phased arrays
Power system harmonics
rotary traveling-wave oscillator (RTWO)
Routing
Tuning
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Summary:In this letter, we propose a 32-42-GHz frequency quadrupler that performs digital logic operations between four phase-shifted differential signals at one-fourth of the output frequency. The four phase-shifted signals are generated via a 10-GHz rotary traveling-wave oscillator (RTWO) and are symmetrically routed to the quadrupler using a CMOS buffered clock tree. The harmonic rejection ratio (HRR) is enhanced by employing a differential LC filter tuned at its output center frequency. The proposed frequency quadrupler is implemented in 22-nm FD-SOI CMOS. At 37 GHz, it produces an output power of -4 dBm with a 10% drain efficiency. It consumes 4 mW from 0.8-V supply and occupies a core area of 0.021 mm2. The worst-case HRR for fundamental, second, third, and fifth harmonics are 41.3, 48.6, 41.3, and 37.3 dBc, respectively.
ISSN:2573-9603
2573-9603
DOI:10.1109/LSSC.2021.3055628