IMPULSE: A 65-nm Digital Compute-in-Memory Macro With Fused Weights and Membrane Potential for Spike-Based Sequential Learning Tasks

The inherent dynamics of the neuron membrane potential in spiking neural networks (SNNs) allows the processing of sequential learning tasks, avoiding the complexity of recurrent neural networks. The highly sparse spike-based computations in such spatiotemporal data can be leveraged for energy effici...

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Bibliographic Details
Published in:IEEE solid-state circuits letters 2021, Vol.4, p.137-140
Main Authors: Agrawal, Amogh, Ali, Mustafa, Koo, Minsuk, Rathi, Nitin, Jaiswal, Akhilesh, Roy, Kaushik
Format: Article
Language:English
Subjects:
CMOS
Cognitive tasks
Compute-in-memory (CIM)
Electric breakdown
Energy efficiency
Learning
Membrane potentials
Membranes
Micromechanical devices
Motion pictures
Neural networks
neuromorphic computing
Neurons
Random access memory
Recurrent neural networks
sentiment analysis
Sparsity
Spikes
spiking neural network (SNN)
SRAM
Static random access memory
Task analysis
Task complexity
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Summary:The inherent dynamics of the neuron membrane potential in spiking neural networks (SNNs) allows the processing of sequential learning tasks, avoiding the complexity of recurrent neural networks. The highly sparse spike-based computations in such spatiotemporal data can be leveraged for energy efficiency. However, the membrane potential incurs additional memory access bottlenecks in current SNN hardware. To that effect, we propose a 10T-SRAM compute-in-memory (CIM) macro, specifically designed for state-of-the-art SNN inference. It consists of a fused weight ( W MEM ) and membrane potential ( V MEM ) memory and inherently exploits sparsity in input spikes leading to ~97.4% reduction in energy-delay product (EDP) at 85% sparsity (typical of SNNs considered in this work) compared to the case of no sparsity. We propose staggered data mapping and reconfigurable peripherals for handling different bit precision requirements of W MEM and V MEM , while supporting multiple neuron functionalities. The proposed macro was fabricated in 65-nm CMOS technology, achieving energy efficiency of 0.99 TOPS/W at 0.85-V supply and 200-MHz frequency for signed 11-bit operations. We evaluate the SNN for sentiment classification from the IMDB dataset of movie reviews and achieve within ~1% accuracy difference and ~ 5× higher energy efficiency compared to a corresponding long short-term memory network.
ISSN:2573-9603
2573-9603
DOI:10.1109/LSSC.2021.3092727