CIFER: A Cache-Coherent 12-nm 16-mm 2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm 2 Synthesizable eFPGA

Saved in:
Bibliographic Details
Published in:IEEE solid-state circuits letters 2023, Vol.6, p.229-232
Main Authors: Li, Ang, Chang, Ting-Jung, Gao, Fei, Ta, Tuan, Tziantzioulis, Georgios, Ou, Yanghui, Wang, Moyang, Tu, Jinzheng, Xu, Kaifeng, Jackson, Paul, Ning, August, Chirkov, Grigory, Orenes-Vera, Marcelo, Agwa, Shady, Yan, Xiaoyu, Tang, Eric, Balkind, Jonathan, Batten, Christopher, Wentzlaff, David
Format: Article
Language:English
Citations: Items that this one cites
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:
ISSN:2573-9603
2573-9603
DOI:10.1109/LSSC.2023.3303111