SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs

Editor's notes: This article introduces a novel debug unit enabling compositional postsilicon validation of heterogeneous SoCs. The unit's effectiveness is demonstrated in post-silicon validation by integrating it into a 12-nm complex SoC prototype. -Mahdi Nikdast, Colorado State Universit...

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Bibliographic Details
Published in:IEEE design and test 2023-12, Vol.40 (6), p.64-75
Main Authors: Tombesi, Gabriele, Zuckerman, Joseph, Mantovani, Paolo, Giri, Davide, Santos, Maico Cassel dos, Jia, Tianyu, Brooks, David, Wei, Gu-Yeon, Carloni, Luca P.
Format: Magazinearticle
Language:English
Subjects:
Computer architecture
Computer bugs
Pins
Prototypes
Registers
Scalability
Silicon
Software
System-on-chip
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Summary:Editor's notes: This article introduces a novel debug unit enabling compositional postsilicon validation of heterogeneous SoCs. The unit's effectiveness is demonstrated in post-silicon validation by integrating it into a 12-nm complex SoC prototype. -Mahdi Nikdast, Colorado State University, USA -Miquel Moreto, Barcelona Supercomputing Center, Spain -Masoumeh (Azin) Ebrahimi, KTH Royal Institute of Technology, Sweden -Sujay Deb, IIIT Delhi, India
ISSN:2168-2356
2168-2364
DOI:10.1109/MDAT.2023.3310355