Demystifying 3D ICs: the pros and cons of going vertical

• Published in: IEEE design & test of computers 2005-11, Vol.22 (6), p.498-510
• Main Authors: Davis, W.R., Wilson, J., Mick, S., Xu, J., Hua, H., Mineo, C., Sule, A.M., Steer, M., Franzon, P.D.
• Format: Article
• Language: English
• Subjects: Assembly; C.0.e System architectures; Delay; Density; Design engineering; Estimates; Fourier transforms; I/O and Data Communications; integration and modeling; Interconnection architectures; Microorganisms; Misalignment; Packaging; Parallel I/O; Placement and routing; Receivers; Routing; Routing and layout; Silicon on insulator technology; Stress; Studies; Three dimensional; Transmitters; Wafer bonding; Wire
• ISSN: 0740-7475; 2168-2356; 1558-1918; 2168-2364
• DOI: 10.1109/MDT.2005.136

This article provides a practical introduction to the design trade-offs of the currently available 3D IC technology options. It begins with an overview of techniques, such as wire bonding, microbumps, through vias, and contactless interconnection, comparing them in terms of vertical density and practical limits to their use. We then present a high-level discussion of the pros and cons of 3D technologies, with an analysis relating the number of transistors on a chip to the vertical interconnect density using estimates based on Rent's rule. Next, we provide a more detailed design example of inductively coupled interconnects, with measured results of a system fabricated in a 0.35-μm technology and an analysis of misalignment and crosstalk tolerances. Lastly, we present a case study of a fast Fourier transform (FFT) placed and routed in a 0.18-μm through-via silicon-on-insulator (SOI) technology, comparing the 3D design to a traditional 2D approach in terms of wire length and critical-path delay.