Leakage Power Analysis and Reduction for Nanoscale Circuits

Leakage current in the nanometer regime has become a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickness scale downward. Various techniques are available to reduce leakage power in high-performance systems

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Bibliographic Details
Published in:IEEE MICRO 2006-03, Vol.26 (2), p.68-80
Main Authors: Amit Agarwal, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy, Kim, C.H.
Format: Article
Language:English
Subjects:
Circuits
CMOS
CMOS technology
Doping profiles
Energy consumption
Leakage
Leakage current
leakage power reduction
Logic design
Maintenance
Nanocomposites
Nanomaterials
nanoscale circuits
Nanoscale devices
Nanostructure
Nanotechnology
Oxides
Subthreshold current
technology scaling
Thickness control
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Description
Summary:Leakage current in the nanometer regime has become a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickness scale downward. Various techniques are available to reduce leakage power in high-performance systems
ISSN:0272-1732
1937-4143
DOI:10.1109/MM.2006.39