RSFQ digital signal processor for interference cancellation

RSFQ high performance digital signal processor capable to perform up to 13 13-bit fixed-point GMACS has been designed for use in successive interference canceller in W-CDMA wireless systems. The performance of the processor has been verified by numerical simulations and VHDL simulation using accurat...

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Bibliographic Details
Published in:IEEE transactions on applied superconductivity 2005-06, Vol.15 (2), p.405-410
Main Authors: Kataeva, I., Hongxia Zhao, Henrik Engseth, Tolkacheva, E., Kidiyarova-Shevchenko, A.
Format: Article
Language:English
Subjects:
Applied sciences
Cancellers
Circuit properties
Clocks
Computer simulation
Design. Technologies. Operation analysis. Testing
Digital
Digital circuits
Digital signal processing
Digital signal processors
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Integrated circuits
Integrated circuits by function (including memories and processors)
Interference
Interference cancellation
Mathematical models
Microprocessors
Multiaccess communication
Multiply-Accumulate Unit
Prototypes
RSFQ
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Shift registers
Signal design
Signal processing
Silicon carbide
successive interference canceller
Superconductivity
Vectors
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Summary:RSFQ high performance digital signal processor capable to perform up to 13 13-bit fixed-point GMACS has been designed for use in successive interference canceller in W-CDMA wireless systems. The performance of the processor has been verified by numerical simulations and VHDL simulation using accurate modeling of the RSFQ gates. Components of the processor, 4 /spl times/ 4 and 5 /spl times/ 5 parallel multipliers, 4 /spl times/ 5, 20 /spl times/ 5 and 4 /spl times/ 15 parallel shift registers have been designed and experimentally tested.
ISSN:1051-8223
1558-2515
DOI:10.1109/TASC.2005.849861