Demonstration of Bit-Serial SFQ-Based Computing for Integer Iteration Algorithms

• Published in: IEEE transactions on applied superconductivity 2015-06, Vol.25 (3), p.1-4
• Main Authors: Qiuyun Xu, Xizhu Peng, Ortlepp, Thomas, Yamanashi, Yuki, Yoshikawa, Nobuyuki
• Format: Article
• Language: English
• Subjects: Acceleration; Algorithm design and analysis; Clocks; Collatz conjecture; Computer architecture; Energy efficiency; Hardware; hardware algorithm; Josephson integrated circuits; LR biasing; Microprocessors; RSFQ; SFQ circuit; superconducting integrated circuits
• ISSN: 1051-8223; 1558-2515
• DOI: 10.1109/TASC.2014.2374454

The Collatz conjecture asserts that by a repeated iteration rule, the operation starting from any positive integer n, eventually produces the value of "1." The main contribution of this paper is to demonstrate a single-flux-quantum (SFQ)-based hardware algorithm that performs an exhaustive search to verify the Collatz conjecture. The circuit consists of a 16-bit integer register, a high-frequency clock generator, and a central processor. This design can perform at up to a maximum clock frequency of 90 GHz with a total power consumption of about 0.85 mW in simulation, based on the AIST 10 kA/cm 2 advanced Nb process. An LR-biasing approach further reduces the power consumption, whereas the computing speed can be accelerated by a factor of 20 when accelerating approaches are adopted. The assessments show that our design can process 2 × 10 7 numbers every second with an energy efficiency of about 5 × 10 10 numbers per Joule.