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Development of Multi-Layer Fabrication Process for SFQ Large Scale Integrated Digital Circuits
We have developed a fabrication technology for superconducting integrated circuits with Nb-based Josephson junctions. The standard fabrication process with 10 mask levels includes 3 Nb superconducting layers and a Mo resistor layer. The influence of deposition parameters on film stress, electrical p...
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Published in: | IEEE transactions on applied superconductivity 2021-08, Vol.31 (5), p.1-4 |
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Main Authors: | , , , , , , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites Items that cite this one |
Online Access: | Get full text |
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Summary: | We have developed a fabrication technology for superconducting integrated circuits with Nb-based Josephson junctions. The standard fabrication process with 10 mask levels includes 3 Nb superconducting layers and a Mo resistor layer. The influence of deposition parameters on film stress, electrical properties, and surface roughness were studied systematically. High quality Nb, Al, Mo, and SiO 2 films were successfully deposited for the subsequent fabrication of circuits. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistance R sh of 2 Ω, followed by the deposition of Nb/Al-AlO x /Nb trilayer Josephson-junction. The target critical current density J c was set at 6 kA/cm 2 . Small-scale circuits such as our standard library cells have been successfully fabricated and tested, confirming the capability of our fabrication technology for superconducting integrated circuits. |
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ISSN: | 1051-8223 1558-2515 |
DOI: | 10.1109/TASC.2021.3065277 |