All-JJ Logic Based on Bistable JJs

The all-JJ logic family is a promising area and power efficient, scalable single flux quantum (SFQ) technology for application to exascale supercomputers. All-JJ superconductive logic is based on a superconductor-ferromagnet-superconductor (SFS) bistable JJ, enabling nanometer feature sizes in VLSI...

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Bibliographic Details
Published in:IEEE transactions on applied superconductivity 2023-08, Vol.33 (5), p.1-7
Main Authors: Jabbari, Tahereh, Bocko, Mark, Friedman, Eby G.
Format: Article
Language:English
Subjects:
all-JJ circuits
Behavioral sciences
Benchmarks
Bias
bistable Josephson junctions
Circuits
Complexity
Critical current density
Current distribution
Delay
Ferromagnetism
Gates (circuits)
Inductance
Inductors
Integrated circuits
Josephson junctions
Junctions
Logic circuits
Logic gates
Parasitics (electronics)
Single flux quantum
superconductive integrated circuits
Superconductivity
Superconductors
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Summary:The all-JJ logic family is a promising area and power efficient, scalable single flux quantum (SFQ) technology for application to exascale supercomputers. All-JJ superconductive logic is based on a superconductor-ferromagnet-superconductor (SFS) bistable JJ, enabling nanometer feature sizes in VLSI complexity superconductive systems. In this paper, a mechanical analogy is proposed to describe the dynamic behavior of these bistable JJs. Novel all-JJ logic gates, such as TFF, DFF, OR, AND, and NOT gates, are presented here. All-JJ circuits are composed of bistable JJs, standard JJs, and bias currents, not requiring large inductors within the storage loops. All-JJ logic cells exhibit less delay and power than standard SFQ cells with the same critical current density. All-JJ systems can operate at high frequencies due to the small capacitance of the SFS JJ. A complex all-JJ circuit from the suite of ISCAS'85 benchmark circuits is also characterized. This complex all-JJ circuit exhibits less delay and power as compared to standard SFQ logic. The bias current in a conventional benchmark circuit and all-JJ benchmark circuit is, respectively, 22 mA and 13 mA. The delay of each cell within the conventional benchmark circuit and all-JJ benchmark circuit is, respectively, approximately 20 and 8 ps. A parasitic inductance in series with the JJs disturbs the current distribution within the all-JJ circuits while degrading the margins. To suppress the effects of this parasitic inductance on SFS JJs, small linear inductors are added to manage the current distribution and improve the parameter margins.
ISSN:1051-8223
1558-2515
DOI:10.1109/TASC.2023.3260774